1. Swaysceptile

    Trouble simulating the output for a VHDL design code

    A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with the help of a testbench generator as well). The output should look something like this: ] I used web application...
  2. xaxxa

    testing on a virutal FPGA

    Hello, I'm trying to learn how to code in VHDL. I already have some basis I learned from school and I want to improve my knowledge in this field. I was wondering if there is any way to test my code on a kind of virtual FPGA. Is there any website or software that allows you to test your code as...
  3. A

    10G Ethernet & Optical transceiver

    Hi, I'm planning to use Intel Stratix 10s inbuilt 10G Hard IP. My questions as follows, 1. Is it rite that we can't use copper ethernet cable for speed greater than 10G, we have to use optical cable only? 2. Optical transceiver - Female connector & optical fiber connector - male which mates...
  4. N

    Can pull-up and pull-down resistors be in the same circuit? (FPGA)

    Hello I need help with FPGA circuit design. I'm using Xilinx Artix-7 XC7A35T. Based on the datasheet/userguide, INIT_B pin must be connected to an external pull-up resistor (4.7kΩ) to ensure clean low to high transition. However, based on the circuit below, we're also connecting the circuit to...
  5. T

    has anyone installed TerosHDL on his VS code on Widwons Subystem Linux?

    I am looking froward on how to install TerosHDL since it looks promising for VHDL programming which includes visual representation of the modules which helps me a lot. does anyone has experience on installing it since I am bit lost on the website step by step instructions? TerosHDL
  6. mazraedar

    Wired communication between two fpga

    Hello everyone, First post here, I'll try to detail my issue as much as possible. So I have two FPGAs, each of them on a different card. Some pinouts communicate via a cable (with a total of 50 pins). The cable is pretty short ( 20 centimeters) and is fully Shielded. The problem beggins when...
  7. Adrienboub

    Code for put number on LCD 4 bits from an input of 32 bits (clk 50MHz)

    Hello, I share my VHDL code for put number of 4 bit on the LCD-4bit of the virtex-6. The input is a biggest numer of 32bit. One state machine for display and another for transmission. ------------------------------------------------------------------------------------------ library IEEE; use...
  8. ashokraj

    For a fpga, how can i determine maximum number of pins I can use for pwm ?

    Hi, I come from the background of microcontroller design. I am learning fpga design. Usually in the ucontrollers the total number of pwm is limited as per the vendors. In FPGA how can i determine the maximum number of pwm I can drive from a fpga. For example, currently i am working with...
  9. ashokraj

    what topics to be covered in python for fpga development and verification?`

    Hi, I am a Hardware engineer. My dream is to be a FPGA engineer/ Digital Design Engineer. I noticed that, some of the job descriptions have python/perl. Learning python completly may not be useful in my domain. Is there any specific topics I will have to focus on in python? or Do I...
  10. S

    FPGA board design with 2 MIPI CSI-2 camera modules at 4k 60FPS

    Hello, I am trying to design an FPGA board that has 2 MIPI cameras on it with 4 data lanes each providing a 4k resolution and 60 FPS data stream to a computer. I am thinking of using a Lattice ECP5 for the FPGA board, but it seems as if its MIPI CSI-2 receiver can only do a max 900 Mbps data...
  11. C

    Array of I2C buses

    Hi! I am new to FPGAs and I am working on a project that involves an array of I2C sensors. I need to record real-time data from all sensors at the exact same time. For now, I am just trying to plan and understand more about how I would do this with an FPGA. For an FPGA such as the LCMXO2...
  12. K

    AHDL Decoder/Driver Help!

    I am trying to change this code that take a 4 bit binary number and converts it to display on a 7 segment display. I now need to alter the code for a 3 bit binary input and a 2 bit binary input as you can see from the hr_tens and min_tens outputs on my clock. Any help is appreciated. Would...
  13. K

    12 Hour Clock Design Help!

    Hello I am having trouble finishing my design for a 12 hour digital clock. I cannot figure out how to connect my final clock to the seven segment displays. I am using a de1 development and using the Quartus II software. I do not need to display the seconds on for mu clock as there are only 4...
  14. super7800

    first fpga schematic and pcb design help

    hello! i am a second year first semester EENG student, and for the digital project this semester we are tasked with programming a fpga to do something (i.e. clock, calculator, stop light, etc). Disclaimer: *the project requirements does not include creating a circuit. most/all are simply using...
Top