fpga

Hi all, We have prototyped our design with icebreaker board. Now we designed a new PCB with just ice40up5k and SPI flash chip. I used this FTDI board to upload my bitstream using radiant programmer. Everything worked perfectly till here, SPI flash is erased, bit stream upload successful, but...

I'm doing a Finite state machine of a elevator using verilog. The elevator contain four states: IDLE, MOVING, ERROR, ALERT * IDLE: When the elevator is stopped. * ERROR: When the elevator's weigth limit is exceeded. * MOVING: When the elevador leaves the current floor and start moving across...

When designing the state machine, do I need to derive a separate output equation for each of the five outputs, or can I group them into the UP signals (U1, U2), the DOWN signals (D1, D2), and the NOGO signal? Assuming this FSM is a Mealy type, what would be the structure of the truth table...

I'm working on an FPGA-based fluence counter project (Z-turn Board V2 Xilinx XC7Z020) that requires designing an electronic board with three high-frequency input signals: 3.3V BNC TTL input. 5V BNC TTL input that is converted to 3.3V TTL using a level shifter. NIM input at -0.8V that is...

I have created a clock glitch generator circuit and I am using RapidWright in order to place it in specific tiles of my device and the end result is a dcp file. My problem is how can I merge this dcp to my existing Vivado project which is a simple aes. Is there a way to create a vivado project...

Hi, currently i am using onsemi RSL10 to communicate with digital accelerometer. Currently it is sampling at 6KHz. I would like to change the acclerometer to a higher G which samples at 25.6KHz. in order to that the current controller does not support because of the limitation of RAM...

Hi everyone, (Please redirect me to the right forum for my question if this is not the right place). I have gone through the process of installing the package of terosHDL on Windows stand lone(my Laptop) via the following link : Installation of terosHDL I had faced three error here, I had just...

Hello all, I am currently working on a project where I have to divide a 100 MHz frequency by n. where n could be any integer1,2,3,4,...9. where I want to give these n integer from external keypad or any software control. Is it possible to do it with #microcontroller based system or FPGA...

Hello guys, This last week I've been learning VHDL using Vivado and a Zybo Z7 I bought. I created an Altitude simulator. It uses LEDS, Buttons and PMOD Double Seven Segment. After I created the code and run it using a tb I decided to upload it into the board but is not working. I'm new to this...

Hello, everyone I want to print characters on LCD with Basys3 I am using xilinx tool and verilog. The LCD screen is illuminated and a square is printed. But characters are not printed How can I solve this problem? help me plz..

Hello everyone, I am looking for an industry experts opinion. About me: I did my bachelors in electronics and communication engineering, master's in computer engineering(learned about FPGA, verilog through courses during masters). I couldnt get job in FPGA domain...

Hi Community, I'm an Application Engineer and I need to design an interposer board that connects to an FPGA module. More specifically, the module is an ALINX AC7100B, which uses Xilinx Artix-7 XC7A100T FPGA. I heard complaints from my colleagues that some FPGAs do not have pads with Schmitt...

I want to divide two 64 bit number and the result will be a float number How I can do this by VHDL?

A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with the help of a testbench generator as well). The output should look something like this: ] I used web application...

Hello, I'm trying to learn how to code in VHDL. I already have some basis I learned from school and I want to improve my knowledge in this field. I was wondering if there is any way to test my code on a kind of virtual FPGA. Is there any website or software that allows you to test your code as...

Hi, I'm planning to use Intel Stratix 10s inbuilt 10G Hard IP. My questions as follows, 1. Is it rite that we can't use copper ethernet cable for speed greater than 10G, we have to use optical cable only? 2. Optical transceiver - Female connector & optical fiber connector - male which mates...

Hello I need help with FPGA circuit design. I'm using Xilinx Artix-7 XC7A35T. Based on the datasheet/userguide, INIT_B pin must be connected to an external pull-up resistor (4.7kΩ) to ensure clean low to high transition. However, based on the circuit below, we're also connecting the circuit to...

I am looking froward on how to install TerosHDL since it looks promising for VHDL programming which includes visual representation of the modules which helps me a lot. does anyone has experience on installing it since I am bit lost on the website step by step instructions? TerosHDL

Hello everyone, First post here, I'll try to detail my issue as much as possible. So I have two FPGAs, each of them on a different card. Some pinouts communicate via a cable (with a total of 50 pins). The cable is pretty short ( 20 centimeters) and is fully Shielded. The problem beggins when...

Hello, I share my VHDL code for put number of 4 bit on the LCD-4bit of the virtex-6. The input is a biggest numer of 32bit. One state machine for display and another for transmission. ------------------------------------------------------------------------------------------ library IEEE; use...