FPGAs (Field Programmable Gate Array)

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Forum for designing, programming and reconfiguring simple and complex FPGAs.
C
Array of I2C buses
Last message by
andrewmm
9
Replies
190
Views
R2R
Quartus Prime megafunction creation
Last message by
cole_maxwell
1
Replies
501
Views
o0danny
Audio interface on FPGA, with "built on plug-ins".
Last message by
andrewmm
1
Replies
134
Views
M
How to get started in FPGA/CPLD
Last message by
mcardoso
17
Replies
1K
Views
asdasd263tg
Help to DRAW Gates please
Last message by
asdasd263tg
6
Replies
249
Views
tindel
Closing timing around a hard multiplier
Last message by
andrewmm
7
Replies
2K
Views
Rufufu
Open sopc builder project with Qsys
Last message by
Rufufu
2
Replies
377
Views
P
Python for Electrical or Electronics Engineering
Last message by
panic mode
6
Replies
2K
Views
ApacheKid
Anyone here actually do meaningful stuff with FPGA devices?
Last message by
soyez
2
20
Replies
3K
Views
Wolframore
Is VHDL still being used?
Last message by
soyez
10
Replies
1K
Views
shaklack
CPLD for project
Last message by
andrewmm
3
Replies
3K
Views
V
Libero 11.9- I am using libero 11.9 with SP2 update
Last message by
Papabravo
2
Replies
476
Views
prophoss
Adding and calling parts
Last message by
prophoss
5
Replies
2K
Views
prophoss
verilog code in VS code?
Last message by
prophoss
0
Replies
352
Views
simozz
FPGA: what is your favourite manufacturer ?
Last message by
Fcathers72
9
Replies
2K
Views
HighVoltageJoe
Converting a high-low signal to an ABZ encoder output using FPGA?
Last message by
MaxHeadRoom
15
Replies
2K
Views
R
UART Receiver in Xilinx Spartan 6 FPGA
Last message by
andrewmm
1
Replies
345
Views
Ahmed Darwish
fpga spartan 6 io ports are no longer working correctly
Last message by
andrewmm
3
Replies
388
Views
J
Use example of Intel University program in Intel Quartus - problem with Board support package?
Last message by
jellypiki
0
Replies
442
Views
prophoss
The enable input
Last message by
prophoss
0
Replies
232
Views
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