# Designing a frequency divider

#### plugnplay

Joined Mar 24, 2022
8
Hello all,

I am currently working on a project where I have to divide a 100 MHz frequency by n. where n could be any integer1,2,3,4,...9. where I want to give these n integer from external keypad or any software control. Is it possible to do it with #microcontroller based system or FPGA system? I tried with D flip flop where I can only get 2^n division factor.

#### MrChips

Joined Oct 2, 2009
29,802
Look up binary rate multiplier. You can also do it with a parallel load counter.

#### dl324

Joined Mar 30, 2015
16,111
I am currently working on a project where I have to divide a 100 MHz frequency by n. where n could be any integer1,2,3,4,...9.
Professionals use PLL's (Phase Locked Loops).

From Signetics:

EDIT: better example showing fractional synthesis.

Last edited:

#### plugnplay

Joined Mar 24, 2022
8
Professionals use PLL's (Phase Locked Loops).

From Signetics:

View attachment 301584
EDIT: better example showing fractional synthesis.
Is it Possible to add 1/n manually in this PLL?

#### Papabravo

Joined Feb 24, 2006
20,588
Is it Possible to add 1/n manually in this PLL?
Signetics is a long defunct company and the particular part described by the block diagram is probably no longer available. Most PLL's will have a provision for a programmable or external divider.

#### dl324

Joined Mar 30, 2015
16,111
Is it Possible to add 1/n manually in this PLL?
Part B of the diagram showed how to do that. You just add a counter in front of the PLL.

BTW, the block diagram isn't for any particular part. It just shows the concept of generating $$f_o=\frac{N}{M}f_i$$. You use whatever you want to implement the functional blocks. I included the company name for proper attribution. The concept is widely used in microprocessors, past and present, to generate clocks.

In the commercial parts I've seen, they include the phase comparator, amplifier, and VCO. You provide the low pass filter and any dividers.

Last edited: