Created a project for my Zybo Z7 - 7010 but it wont work.

stryker1803 · Aug 11, 2023

Hello guys,

This last week I've been learning VHDL using Vivado and a Zybo Z7 I bought. I created an Altitude simulator. It uses LEDS, Buttons and PMOD Double Seven Segment. After I created the code and run it using a tb I decided to upload it into the board but is not working. I'm new to this field so is hard for me to figure out and I can't seem to find helpful info on this. I will leave the code below with constraints and warnings.

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity F15_Altitude_Warning_System is
-- Port ( );
Port(CLK : in std_logic;
Control_UP : in std_logic;
Control_Down: in std_logic;
J1_mod : out std_logic_vector (6 downto 0);
J2_mod : out std_logic_vector (6 downto 0);
Warning_R : out std_logic;
Good_G : out std_logic);
--Declara seven segment como output

end F15_Altitude_Warning_System;

architecture Behavioral of F15_Altitude_Warning_System is

signal Seven_segment_J1 : std_logic_vector (6 downto 0);
signal Seven_segment_J2 : std_logic_vector (6 downto 0);
signal counter : integer := 0;
begin

Process(CLK)
begin

if rising_edge(CLK) then
if Control_UP = '1' then
if counter < 7 then
counter <= counter + 1;
end if;
end if;

case counter is
when 1 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0000110";
Good_G <= '1';
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 2 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1011011";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 3 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1001111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 4 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1100110";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 5 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1101101";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 6 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1111101";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 7 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0000111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
Warning_R <= '1';
when others =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0111111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '0';
Warning_R <= '0';
end case;
end if;

end process;

Constraints:

##Clock signal
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { CLK }];

##Buttons
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { Control_UP[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { Control_Down[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

##LEDs
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { Good_G[0] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

##RGB LED 6
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { Warning_R_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { Green_G_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

#Pmod Header JC
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]

#Pmod Header JD
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { J2_modjd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]

Warnings:

[Place 30-58] IO placement is infeasible. Number of unplaced IO Ports (2) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 2 sites.
Term: Control_Down
Term: and Control_UP

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 0 | 0 | | | | | | |
| 34 | 50 | 8 | LVCMOS33(8) | | | +3.30 | YES | |
| 35 | 50 | 1 | LVCMOS33(1) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 100 | 9 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34 | J1_mod[0] | LVCMOS33 | IOB_X0Y30 | V15 | |
| | J1_mod[1] | LVCMOS33 | IOB_X0Y29 | W15 | |
| | J1_mod[2] | LVCMOS33 | IOB_X0Y48 | T11 | |
| | J1_mod[3] | LVCMOS33 | IOB_X0Y47 | T10 | |
| | J2_mod[0] | LVCMOS33 | IOB_X0Y40 | T14 | |
| | J2_mod[1] | LVCMOS33 | IOB_X0Y39 | T15 | |
| | J2_mod[2] | LVCMOS33 | IOB_X0Y38 | P14 | |
| | J2_mod[3] | LVCMOS33 | IOB_X0Y37 | R14 | * |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | CLK | LVCMOS33 | IOB_X0Y76 | K17 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Ian Rogers · Aug 11, 2023

I know nothing about FPGA's but read here!
https://support.xilinx.com/s/question/0D52E00006hpsXBSAY/lvcmos33-with-vcco-18v?language=en_US
You may need to upgrade Vivado.

drjohsmith · Aug 13, 2023

stryker1803 said:
Hello guys,

This last week I've been learning VHDL using Vivado and a Zybo Z7 I bought. I created an Altitude simulator. It uses LEDS, Buttons and PMOD Double Seven Segment. After I created the code and run it using a tb I decided to upload it into the board but is not working. I'm new to this field so is hard for me to figure out and I can't seem to find helpful info on this. I will leave the code below with constraints and warnings.

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity F15_Altitude_Warning_System is
-- Port ( );
Port(CLK : in std_logic;
Control_UP : in std_logic;
Control_Down: in std_logic;
J1_mod : out std_logic_vector (6 downto 0);
J2_mod : out std_logic_vector (6 downto 0);
Warning_R : out std_logic;
Good_G : out std_logic);
--Declara seven segment como output

end F15_Altitude_Warning_System;

architecture Behavioral of F15_Altitude_Warning_System is

signal Seven_segment_J1 : std_logic_vector (6 downto 0);
signal Seven_segment_J2 : std_logic_vector (6 downto 0);
signal counter : integer := 0;
begin

Process(CLK)
begin

if rising_edge(CLK) then
if Control_UP = '1' then
if counter < 7 then
counter <= counter + 1;
end if;
end if;

case counter is
when 1 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0000110";
Good_G <= '1';
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 2 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1011011";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 3 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1001111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 4 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1100110";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 5 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1101101";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 6 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "1111101";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
if Control_Down = '1' then
Seven_segment_J1 <=(others => '0');
end if;
when 7 =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0000111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '1';
Warning_R <= '1';
when others =>
Seven_segment_J1 <= "0111111";
Seven_segment_J2 <= "0111111";
J1_mod <= Seven_segment_J1;
J2_mod <= Seven_segment_J2;
Good_G <= '0';
Warning_R <= '0';
end case;
end if;

end process;

Constraints:

##Clock signal
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { CLK }];

##Buttons
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { Control_UP[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { Control_Down[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]

##LEDs
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { Good_G[0] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

##RGB LED 6
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { Warning_R_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { Green_G_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

#Pmod Header JC
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { J1_mod[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]

#Pmod Header JD
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { J2_mod[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { J2_modjd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]

Warnings:

[Place 30-58] IO placement is infeasible. Number of unplaced IO Ports (2) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 2 sites.
Term: Control_Down
Term: and Control_UP

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 0 | 0 | | | | | | |
| 34 | 50 | 8 | LVCMOS33(8) | | | +3.30 | YES | |
| 35 | 50 | 1 | LVCMOS33(1) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 100 | 9 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34 | J1_mod[0] | LVCMOS33 | IOB_X0Y30 | V15 | |
| | J1_mod[1] | LVCMOS33 | IOB_X0Y29 | W15 | |
| | J1_mod[2] | LVCMOS33 | IOB_X0Y48 | T11 | |
| | J1_mod[3] | LVCMOS33 | IOB_X0Y47 | T10 | |
| | J2_mod[0] | LVCMOS33 | IOB_X0Y40 | T14 | |
| | J2_mod[1] | LVCMOS33 | IOB_X0Y39 | T15 | |
| | J2_mod[2] | LVCMOS33 | IOB_X0Y38 | P14 | |
| | J2_mod[3] | LVCMOS33 | IOB_X0Y37 | R14 | * |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | CLK | LVCMOS33 | IOB_X0Y76 | K17 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

th error is saying you want to conect a signal in oyour code to a pin that is not vailable,
the "easy" way to debug, is to comment out all pin constraints, and see if it fits,
then put the constraints back in in groups till you find th eones that fail.
Also , you have a clock, you must include a clock frequency constrain in your desing as an absolute minimum
you should also include the IO timming constraints, but get the above working first

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Created a project for my Zybo Z7 - 7010 but it wont work.

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Created a project for my Zybo Z7 - 7010 but it wont work.

stryker1803

Ian Rogers

drjohsmith

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