1. Swaysceptile

    Trouble simulating the output for a VHDL design code

    A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with the help of a testbench generator as well). The output should look something like this: ] I used web application...
  2. xaxxa

    testing on a virutal FPGA

    Hello, I'm trying to learn how to code in VHDL. I already have some basis I learned from school and I want to improve my knowledge in this field. I was wondering if there is any way to test my code on a kind of virtual FPGA. Is there any website or software that allows you to test your code as...
  3. T

    has anyone installed TerosHDL on his VS code on Widwons Subystem Linux?

    I am looking froward on how to install TerosHDL since it looks promising for VHDL programming which includes visual representation of the modules which helps me a lot. does anyone has experience on installing it since I am bit lost on the website step by step instructions? TerosHDL
  4. Adrienboub

    Code for put number on LCD 4 bits from an input of 32 bits (clk 50MHz)

    Hello, I share my VHDL code for put number of 4 bit on the LCD-4bit of the virtex-6. The input is a biggest numer of 32bit. One state machine for display and another for transmission. ------------------------------------------------------------------------------------------ library IEEE; use...
  5. J

    Issue implementing counter in VHDL

    Hi everyone, I have just started using VHDL and I am trying to understand a piece of code I code I was handed. The counter must count up to 0xBEBC200 (which is equal to 200,000,000) and whenever there is a change in the clock signal, the program will enter the process statement to assess wether...
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