Design of a parking management system

The goal of our system is to manage the availability of parking spaces. This system has 4 input signals (mode in): the entry-exit captures of type std_logic, the clock, and the maximum number of spaces in the parking lot (4-bit binary word of type std_logic_vector). The sensor inputs are used to increment or decrement the counter (4 bits). The counter output is compared to the maximum number of spaces in the parking lot. The output signals (mode out) are:

• PD = 1 if there are still available spaces, otherwise PD = 0 (type std_logic).
• PC = 1 if the parking lot is full, otherwise PC = 0 (type std_logic).

1) VHDL Entity and Architecture for a 4-bit Counter and Comparator in a Parking Management System



Im stuck on doing the structural design of this system, also i want someone to check if my answers to the previous question is valid enough, thanks