Dear all,
I am working on an RF power amplifier designed to operate at 13.56 MHz. I am using the ADuM4221A gate driver IC in my circuit. The issue I am facing is that the output signal from the driver is not correct. More importantly, even the input signals at pins VIA and VIB are not as expected. According to the datasheet and my understanding, these two input signals should be 180 degrees out of phase with each other. However, after running the simulation in LTspice, I am not getting the required phase relationship. I have attached my .asc file for your reference. I would be very grateful if any of the experienced members in this group could kindly take a look at my circuit and guide me on what might be going wrong. Thank you very much in advance for your time and help.

 

LD1 &LD2 What value? uH or uF What is that? Are you trying to resonate LD1 and Cs1?
CGS1 should be connected G to S of M1.
D1 is upside down.
D3 is upside down and should connect G-S of M1.
L2 is ac shorted out.
U1 pin VDDA is wrong. Why 470nF? Diode is backwards.

 

Here is an example. T2 is center tapped. I know it does not look that way but it is.

Another example. The CT output transformer is easy to see this time.

 

I am working on an RF power amplifier designed to operate at 13.56 MHz. I am using the ADuM4221A gate driver IC in my circuit.

I think the Gate Driver is too slow to work at 13mHz.

The Gate Driver was designed to receive square wave signals. You might use two signals sources that are 90 degrees out of phase and drive directly into the inputs. I would use a square wave from 0V to 3V while the other input gets 3V to 0V.

 

I think the Gate Driver is too slow to work at 13mHz.

The Gate Driver was designed to receive square wave signals. You might use two signals sources that are 90 degrees out of phase and drive directly into the inputs. I would use a square wave from 0V to 3V while the other input gets 3V to 0V.

Dear ronsimpson,

Thank you very much for your kindness and prompt reply. I truly appreciate the time and guidance you have offered. I have made the following corrections based on your suggestions:

1. The LD1 and LD2 RF choke inductors were incorrectly marked as µF. The correct value is 47 µH, and I have updated it in the schematic.
2. CGS1 has also been corrected.
3. D1 and D3 are now connected in reverse bias as you recommended.

Regarding L2, I would like to kindly seek clarification. By removing VDD, do you mean that I should connect it to ground instead? (Updated schmatic is attached for your kind reference, please.)

For your reference, VDDA supplies the high‑side driver from an isolated +12 V rail. Cbs (470 nF) is the bootstrap capacitor, and Dbs (1N4148) is a Zener diode intended to allow current to flow downward. If this approach is incorrect, could you please guide me further?

I think the phase splitter and the gate driver stage are not working properly. At the input of both MOSFETs (M1 & M2), no signal, just a few uV (DC). How can we make it correct with the correct approach?

Thank you once again for your valuable support.

 

Dear all,
I am working on an RF power amplifier designed to operate at 13.56 MHz. I am using the ADuM4221A gate driver IC in my circuit. The issue I am facing is that the output signal from the driver is not correct. More importantly, even the input signals at pins VIA and VIB are not as expected. According to the datasheet and my understanding, these two input signals should be 180 degrees out of phase with each other (with the same magnitude). However, after running the simulation in LTspice, I am not getting the required phase relationship (also, the magnitude is different). I have attached my .asc file (in the previous post, Post #5) for your reference. I would be very grateful if any of the experienced members in this group could kindly take a look at my circuit and guide me on what might be going wrong. Thank you very much in advance for your time and help.

 

Regarding L2, I would like to kindly seek clarification. By removing VDD, do you mean that I should connect it to ground instead? (Updated schmatic is attached for your kind reference, please.)

Cb1 & Cb2 should be in parallel not series.
Cb is from VDD to GND. You have Cb across L2. At 13MHz Cb is a short.

 

Aside from the other comments, that 90 degrees is wrong!!
In a push/pull amplifier the signals are 180 degrees offset. that is so that the two stages are not in conflict, but alternating in conduction. The circuit we see in post #2 is drawn, not in any way designed. It includes other errors in addition to those described in the posts that followed it.
The circuits shown in post #3 do not show errors, although they may not suit the application intended in post#1.
I am not able to open any ".asc" files to see the circuit, because I don't have that simulator software.
Can you post a screen shot?

 

Remove Cbs.
Make Cb1 & Cb2 parallel.
M1 the Gate Driver is applying drive G-S.
M2 the Gate Driver is applying drive not G-S but has LD2 in the loop. This probably will oscillate. Maybe put L2 on the Drain.

 

Cb1 & Cb2 should be in parallel not series.
Cb is from VDD to GND. You have Cb across L2. At 13MHz Cb is a short.
View attachment 367409

Sure, Sir, I will place them in parallel and observe the behavior. Then I will share the results here, no matter what they turn out to be.

 

The ADuM4221A is digital not analog. You input a sine wave. It was designed to have square wave inputs. The outputs cannot be sine wave. Is your goal to have the MOSFETs to be 100% of or 100% off?

 

This GND shorts out the output. Remove it.

 

Aside from the other comments, that 90 degrees is wrong!!
In a push/pull amplifier the signals are 180 degrees offset. that is so that the two stages are not in conflict, but alternating in conduction. The circuit we see in post #2 is drawn, not in any way designed. It includes other errors in addition to those described in the posts that followed it.
The circuits shown in post #3 do not show errors, although they may not suit the application intended in post#1.
I am not able to open any ".asc" files to see the circuit, because I don't have that simulator software.
Can you post a screen shot?

Thank you so much for your kind response and help. Yes, you are right, the signals must be 180 degrees out of phase. That is why I mentioned 180 degrees in all my posts. Below is the screenshot for your kind review. If you have any other topology in mind, please let me know. I am happy to try it. My only goal is to make the circuit work as described in Post #1 and Post #6.
Thank you again for your guidance.

 

Remove Cbs.
Make Cb1 & Cb2 parallel.
M1 the Gate Driver is applying drive G-S.
M2 the Gate Driver is applying drive not G-S but has LD2 in the loop. This probably will oscillate. Maybe put L2 on the Drain.
View attachment 367410

You are right, sir. I will remove LD2; it will oscillate. I also need to remove the Cbs (470nF) at the Pin VDDA,right sir?

 

The ADuM4221A is digital not analog. You input a sine wave. It was designed to have square wave inputs. The outputs cannot be sine wave. Is your goal to have the MOSFETs to be 100% of or 100% off?

50% ON and 50% OFF

 

Dear Sir,
Thank you very much for your continued guidance. I have implemented all the changes you suggested, but unfortunately there is no improvement in the signals. I removed Cbs and also disconnected VDDA and GNDA. I also removed inductor LD2 from the source of M2. Still, the output remains DC, and the voltage at the transformer output is 0V.
If you could kindly suggest a suitable input stage and driver stage for this 13.56 MHz power amplifier, I would be more than happy to use it. I am ready to try any topology that can work. I feel the input and driver stage in my current circuit may be the issue. Ideally, I would like to use a single 13.56 MHz source (3V–5V) and then add some input buffer, splitter, and phase shifter stages before the amplifier. Using two separate 180‑degree out‑of‑phase signal sources is not feasible. I look forward to your kind advice.

 

There is still the serious problem in the circuit shown that Vdd is applied to the junction of L1 and L2, the bottom of L2 is tied directly to the common, thus a direct connection of Vdd to common.
For the operati in of the circuit as shown, Vdd must not connect to any part of that transformer scheme
ALSO, the connection to system common on the line to VswA must be removed.

 

There is still the serious problem in the circuit shown that Vdd is applied to the junction of L1 and L2, the bottom of L2 is tied directly to the common, thus a direct connection of Vdd to common.
For the operati in of the circuit as shown, Vdd must not connect to any part of that transformer scheme
ALSO, the connection to system common on the line to VswA must be removed.

Dear Sir, If I remove the VDD connection from the transformer, should I keep that junction empty and leave it unconnected? Below is the screenshot for your reference. Is this what you meant?

 

I think the Gate driver will not respond to 30nS pulses.
Here I used two inputs V1 and V2.

 

I think the Gate driver will not respond to 30nS pulses.
Here I used two inputs V1 and V2.
View attachment 367415

Dear Sir, In your opinion, what should I do in this case? As I mentioned earlier, I prefer to use a single 13.56 MHz source (3V–5V) and then add an input buffer, a splitter, and a phase shifter stage before the amplifier. Can the current topology be modified to work with this driver stage, or should I change it completely? I look forward to your kind guidance.