Issue implementing counter in VHDL

Thread Starter

jefazo92

Joined Mar 26, 2017
3
Hi everyone,

I have just started using VHDL and I am trying to understand a piece of
code I code I was handed. The counter must count up to 0xBEBC200 (which
is equal to 200,000,000) and whenever there is a change in the clock
signal, the program will enter the process statement to assess wether
the counter has reached 0xBEBC200 and reset the counter and if not,
increase the counter by 1. However, my friend has put the increment
statement inside the if statement assessing whether 0xBEBC200 has been
reached or not. For me this makes no sense since this means the counter
will not be incremented unless it is equal to 0xBEBC200. He has told me
the code is alright but could someone please tell me if the code is
right or not ? Thanks.

P.d. The clock is 100MHz and this section of the code acts as delay in a
larger system. The code segement can be found in the Delay.txt file attached,
 

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Wolframore

Joined Jan 21, 2019
1,321
if counter <= final number -- perhaps the confusion is the “<=“ symbol which is equivalent to “less than or equal to“
advance counter. -- add 1

else -- the counter > final number
restart -- reset counter to 0

i was worried about starting VHDL but it looks very similar to C
 
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