Trouble simulating the output for a VHDL design code

Thread Starter


Joined Oct 28, 2021
A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with the help of a testbench generator as well). The output should look something like this:


I used web application called EDA Playground for simulation. Below is the link of it whicn includes both the design and testbench code:

Kinda new to this. Don't know why it doesn't run.

Is there supposed to be a proper sequence of inputs for this specific code or am I missing some other inputs, such as those in testbench stimuli?

Hope someone could help analyzing the design and what I should put in the testbench stimuli cause I think I'm missing something. Been doing this for days and still couldn't make it run. Feel free to try the simulation.