1. itskrish

    test bench code

    hi this is my vlsi term project (stop watch) can anyone help me generating the test bench code in vhdl
  2. VasantJ3

    Is there a way to make the verilog port declaration based on a MACRO value

    Basically, what I am trying to achieve is that, There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized. But I also want to create dedicated output ports from each of these registers. The number of registers is based on the REG_COUNT macro value...
  3. T

    I want to print characters on LCD with Basys3 board

    Hello, everyone I want to print characters on LCD with Basys3 I am using xilinx tool and verilog. The LCD screen is illuminated and a square is printed. But characters are not printed How can I solve this problem? help me plz..
  4. Swaysceptile

    Trouble simulating the output for a VHDL design code

    A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with the help of a testbench generator as well). The output should look something like this: ] I used web application...
  5. M

    Analog Mixed Signal Validation Engineer, position wanting in Sanford NC

    Brief introduction: With 20 years of experience in IC chip design, we are a professional supplier of products and solutions for the industrial-grade general MCU, BLE SoC, and domestic leading IIoT SoC-eSE security SoC. Our RD center is in Sanford, NC 27332. Title:Analog Mixed Signal Validation...