Is there a way to make the verilog port declaration based on a MACRO value

Thread Starter

VasantJ3

Joined Nov 3, 2023
1
Basically, what I am trying to achieve is that,
There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized.

But I also want to create dedicated output ports from each of these registers. The number of registers is based on the REG_COUNT macro value, so is there a way to make the output ports also get initialized based on the macro value count?

Similar to how generate works in Verilog, but sadly generate cannot be used for port declarations.


I tried many ways, but I am stuck and cannot seem to get any idea on how to solve this. Any insight would be appreciated.


Code:
`define REG_COUNT 12'h008 // for a total of 8 registers to be declared.

module md_regbank(
//Since macro value is for 8 registers, I need 8 output ports to be declared here


);

 reg [7:0] register[12'h000:`REG_COUNT];   // 8 registers are there

 always @() begin
 ...............
 end
endmodule
 
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