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Verilog D-Flip Flop Counter

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bobsbugsbegone

Joined Nov 17, 2024
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Hello all,
I'm currently attempting to build a 4-bit D-Flip Flop counter to go through a sequence of numbers (5 -> 0 -> 9 -> 3) in Verilog with a structural design. The counter simply needs to go through the sequence and when reset, begin again at 5. I was wondering if I could receive any guidance for this design, as I'm simply not sure where to begin. Any advice is greatly appreciated. Thank you!
 
WBahn

WBahn

Joined Mar 31, 2012
32,703
Start forgetting about HDL until you have your design for the counter (since you are doing the HDL structurally and no behaviorally).

Design a four bit counter that does what you need and then translate the schematic into a structural HDL description.
 
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