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Verilog : It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to 4, why?? Please give me the solution as a code and explaination for it if possible.
It's supposed to be a MOD10 counter, so I expected for it to count from 0 to 9 and reset to 0 again but it counts from 0 to 9 and resets to 4.
module MOD10 (clk, clr, q);
input clk, clr;
output [3:0] q;
wire x, w;
assign x = q[3] & q[1]; // Detects when the count reaches 10 (binary 1010)
assign w = x | clr; // Reset or clear condition
TFF tff1(clk, w, 1'b1, q[0]); // First TFF for q[0]
TFF tff2(q[0], w, 1'b1, q[1]); // Second TFF for q[1]
TFF tff3(q[1], w, 1'b1, q[2]); // Third TFF for q[2]
TFF tff4(q[2], w, 1'b1, q[3]); // Fourth TFF for q[3]
endmodule
module TFF (clk, clr, t, q);
input clk, clr, t;
output reg q;
always @(posedge clr or negedge clk) begin
if (clr)
q <= 0; // Clear or reset the flip-flop
else begin
if (!t)
q <= q; // Maintain the state when T = 0
else
q <= ~q; // Toggle the output when T = 1
end
end
endmodule
module MOD10_TB();
reg clk, clr;
wire [3:0] q;
// Instantiate the MOD10 module
MOD10 uut (clk, clr, q);
// Clock signal generation (50% duty cycle)
initial begin
clk = 0;
forever #5 clk = ~clk; // Toggle clock every 5 time units
end
// Reset logic and test sequence
initial begin
clr = 1; // Reset active
#10 clr = 0; // Deactivate reset after 10 time units
#110 $finish; // End simulation after 110 time units
end
endmoduleIt's supposed to be a MOD10 counter, so I expected for it to count from 0 to 9 and reset to 0 again but it counts from 0 to 9 and resets to 4.
