vlsi

Verilog : It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to 4, why?? Please give me the solution as a code and explaination for it if possible. module MOD10 (clk, clr, q); input clk, clr; output [3:0] q; wire x, w; assign x = q[3] & q[1]; //...

hi this is my vlsi term project (stop watch) can anyone help me generating the test bench code in vhdl

Hello everyone, I'm having difficulty simulating CADENCE, NMOS AND PMOS components are NOT enabled when making modifications, such as inserting values of width or length of their structures in the schematic [schematic]. It is impossible to do the simulation. And in the layout there is no icon...