Anyone knows how to automatically generate an n-bit carry lookahead adder in verilog?

I've been trying to make a generic module in verilog that takes n as a parameter and makes a carry-lookahead adder, I thought it would be pretty useful but I couldn't find any working specification for it online.

The module I've written doesn't work because of a part-select error. I wondered if anyone in here knew how to make it work or implement it differently.
Here's my code, right now it errs out with "kk is not a constant" at line "c[k+1]|=&p[k:kk]&g[kk-1];" which is error 10734 if anyone wants to check.

module cla (
input cin,
input [n-1:0] x,
input [n-1:0] y,
output reg [n-1:0] s,
output reg cout);

parameter n=8;
reg [n:0] c;
reg [n-1:0] p,g;
integer k,kk;

always @*
begin
c[0]=cin;
for (k=0;k<n;k++)
begin
s[k]=x[k]^y[k]^c[k];
p[k]= x[k] | y[k];
g[k]= x[k] & y[k];
c[k+1]=g[k];
for (kk=k;kk>0;kk--)
begin
c[k+1]|=&p[k:kk]&g[kk-1];
end
c[k+1]|=&p[k:0]&cin;
end
cout=c[n];
end
endmodule

For some reason this works in Yosys, but not in Quartus.