Here is my Hardware Interlock Circuit for Gate Signals which prevents both PWM Signals to be at same state at any given time. Here I want to reduce this two AND Gate IC's into a Single AND Gate IC.
Or Is there any other way to implement the Hardware Interlock for Gate Signals ?
Is there any other way to do that ?
Is there any AND Logic IC's which has 6 channels of 3 input AND Gate ?
Note: The Gate Signals are there to drive the Lower and Upper IGBT of Same Leg in Inverter.
My another doubt is, The PWM will be switching at 20kHz. So will there be any significant Latency introduced with this Interlock Circuit. or What parameters should I look for If I have to see whether this Logic IC will support this much frequency of switching?

 

Or Is there any other way to implement the Hardware Interlock for Gate Signals ?

Use a driver IC that has a single PWM input instead of separate High and Low inputs. They are known as Half-Bridge Drivers instead of High-side/Low-side drivers. Examples are FAN73932, IR2184

 

Your drawing style creates unintelligible schematics.

 

Use a driver IC that has a single PWM input instead of separate High and Low inputs.

Ok for driving small MOSFETs, but the huge gate capacitance on large MOSFETs means that some driver ICs provide insufficient dead-time to prevent shoot-through. The IR2184 provides no inherent dead-time. Separate Hin and Lin inputs allow dead-time to be customised.

 

The IR2184 provides no inherent dead-time.

500ns with on the normal version, variable between 500ns and 6us on the "4" version.

 

We don't draw circuit schematics with IC pin diagrams. We use logic gate symbols.

 

We don't draw circuit schematics with IC pin diagrams. We use logic gate symbols.

View attachment 270503

Invert C and its a 3-input NOR gate.

 

Here is my Hardware Interlock Circuit for Gate Signals which prevents both PWM Signals to be at same state at any given time. Here I want to reduce this two AND Gate IC's into a Single AND Gate IC.

That won't do what you apparently want (non-overlapping signals).
If the upper leg is high and the lower leg goes high, the UL output will be high (along with the LL) during the propagation delay of the inverter and the upper AND gate.

See LTspice simulation below (green trace and purple trace)

A circuit using a cross-coupled latch will guarantee two non-overlapping outputs (red trace and yellow trace):