I was reading this discussion - Interlock Discussion, because I want to design a Half Bridge MOSFET driver, with interlock. I recreated both the circuits in LTspice that were recommended
The logic I want is -
In1 In2 Op
0 0 both OFF
1 0 Up MOS ON, BOT MOS OFF
0 1 Up MOS ON, BOT MOS OFF
1 1 Both MOS OFF (no shoot through/no oscillation)
Undesirable characteristics

1. For the NOR circuit I am getting oscillations when both inputs are low. I need a stable OFF state.
2.For the AND+NOT circuit I am seeing sudden/momentary a spike when both inputs go hi. I need both to be OFF.
Is there a way to get the logic I want using the circuits mentioned in the above discussion?
The logic I want is -
In1 In2 Op
0 0 both OFF
1 0 Up MOS ON, BOT MOS OFF
0 1 Up MOS ON, BOT MOS OFF
1 1 Both MOS OFF (no shoot through/no oscillation)
Undesirable characteristics

1. For the NOR circuit I am getting oscillations when both inputs are low. I need a stable OFF state.
2.For the AND+NOT circuit I am seeing sudden/momentary a spike when both inputs go hi. I need both to be OFF.
Is there a way to get the logic I want using the circuits mentioned in the above discussion?
