Hardware Interlock Circuit - oscillations seen when both input are in phase

Thread Starter

Sud_09

Joined Jul 25, 2023
3
I was reading this discussion - Interlock Discussion, because I want to design a Half Bridge MOSFET driver, with interlock. I recreated both the circuits in LTspice that were recommended

The logic I want is -
In1 In2 Op
0 0 both OFF
1 0 Up MOS ON, BOT MOS OFF
0 1 Up MOS ON, BOT MOS OFF
1 1 Both MOS OFF (no shoot through/no oscillation)

Undesirable characteristics
1776953522830.png
1. For the NOR circuit I am getting oscillations when both inputs are low. I need a stable OFF state.
2.For the AND+NOT circuit I am seeing sudden/momentary a spike when both inputs go hi. I need both to be OFF.

Is there a way to get the logic I want using the circuits mentioned in the above discussion?
 

schmitt trigger

Joined Jul 12, 2010
2,056
For the Cross-coupled flip-flops, on a truth table with four possible input states, there is a state where it becomes unstable or indeterminate.
This is precisely what you’re seeing.
 

Thread Starter

Sud_09

Joined Jul 25, 2023
3
For the Cross-coupled flip-flops, on a truth table with four possible input states, there is a state where it becomes unstable or indeterminate.
This is precisely what you’re seeing.
I understand. But the AND+NOT gate circuit shows a spike at ~5uS, which is also unacceptable(Both ON = shoot-through). Is there a work around?
 

crutschow

Joined Mar 14, 2008
38,418
The glitch you are seeing with the top circuit is from the inverter circuit delay at the AND gate input.

How about using an XOR gate to generate the interlock signal?
Its output is low when both inputs are either high or low, and high otherwise, with no glitches if the inputs change states at the same time (red trace, LTspice sim below).

If you want an inverted output, you can use the CD4077 XNOR gate (blue trace).

1776974825595.png
 
Last edited:

MisterBill2

Joined Jan 23, 2018
27,321
Another option to avoid the inconvenience of the spikes is to use an actual flipflop IC, such as the CD4013. THAT avoids the issue completely.
AND UNDERSTAND that with all 4000 series CMOS devices, EVERY input, including unused sections MUST be held at a valid logic level, not floating. Neglecting to do that WILL cause problems.
 

MisterBill2

Joined Jan 23, 2018
27,321
@MisterBill2 Are you asking me to use the CD4013 with my 2 circuits in the question that I asked? Or are you asking me to use the DFF with @crutschow circuit?
Appreciate the help.
I am stating the reality that using an actual flipflop for that function would avoid the unintended results that you get with a FF assembled from IC logic elements.
Consider that you are not the first person to discover that it is not always as simple as it looks like it should be. THAT is why there is more circuit inside the CD4013 than you would imagine. Trust me on that! Logic ICs are rather complex inside.
 

MisterBill2

Joined Jan 23, 2018
27,321
It happens that many of the technical challenges that we run into are not the first time this challenge has occured, and that often, but not always, a solution has been found and implemented.
 
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