Here is my Hardware Interlock Circuit for Gate Signals which prevents both PWM Signals to be at same state at any given time. Here I want to reduce this two AND Gate IC's into a Single AND Gate IC.
Or Is there any other way to implement the Hardware Interlock for Gate Signals ?
Is there any other way to do that ?
Is there any AND Logic IC's which has 6 channels of 3 input AND Gate ?
Note: The Gate Signals are there to drive the Lower and Upper IGBT of Same Leg in Inverter.
My another doubt is, The PWM will be switching at 20kHz. So will there be any significant Latency introduced with this Interlock Circuit. or What parameters should I look for If I have to see whether this Logic IC will support this much frequency of switching?