According to theory the time period for ramp signal generated using the following circuit should be:
\[ \frac{2}{3} \frac{V_{CC}.C_{1}.R_{1}.(R_{1}+R_{2})}{V_{CC}.R_{2}-V_{BE}.(R_{1}+R_{2})} \]

Now... putting the value of Vcc, R1, R2, VBE, RE... the time period comes out to be around 0.9ms.
But from the simulation it appears to be around 3ms.

 

Please ignore the values on the hand-drawn circuit attachment. The value i calculated by formula was by taking R1,R2,Vcc,VBE, C1 same as in the spice simulation.

 

Does the voltage at the junction of R1 and R2 look wrong to you?
Plot it and see what it does.
Where is Re in your equation?

 

Does the voltage at the junction of R1 and R2 look wrong to you?
Plot it and see what it does.
Where is Re in your equation?

According to theory the time period for ramp signal generated using the following circuit should be:
\[ \frac{2}{3} \frac{V_{CC}.C_{1}.R_{1}.(R_{1}+R_{2})}{V_{CC}.R_{2}-V_{BE}.(R_{1}+R_{2})} \]

Now... putting the value of Vcc, R1, R2, VBE, RE... the time period comes out to be around 0.9ms.
But from the simulation it appears to be around 3ms.
View attachment 266763View attachment 266764

im sorry its ...
\[ \frac{2}{3} \frac{V_{CC}.C_{1}.R_{E}.(R_{1}+R_{2})}{V_{CC}.R_{2}-V_{BE}.(R_{1}+R_{2})} \]

 

Does the voltage at the junction of R1 and R2 look wrong to you?
Plot it and see what it does.
Where is Re in your equation?

im sorry its ...
\[ \frac{2}{3} \frac{V_{CC}.C_{1}.R_{E}.(R_{1}+R_{2})}{V_{CC}.R_{2}-V_{BE}.(R_{1}+R_{2})} \]
yea it should be ~3.4V its showing 4.3V
but when i plotted it its showing a 3.4V signal

 

To minimize the effects of transistor beta variation and transistor Vbe change with temperature, you can use a two-transistor current-mirror to generate the constant current (below), that only requires one resistor to establish the charging current :
The capacitor charging current is nearly (ideally) the same as the current through R5.