Hi, I found myself in a situation like this:


I don't have a good solution how to get out of it. Simple switching either component to top/bottom layer will cause other pairs to cross. Same if I rotate their relative positions. The only solution that untangles it is this:


However, I wonder if this will have a chance to work? I am concerned about the signal impedance discontinuity. Maybe I should all ground vias next to both passing vias? Both blue and red traces will have a solid gnd plane right below. This signal is 1,5ghz.

 

If that crossover effects the proper operation of your design, I'll buy you a beer.

Edit: I'm not an expert at 1.5GHz, but I am an expert at beer.

 

@joeyd999, heh, are you say nothing to worry about right? Not an expert on 1.5Ghz then how can you advise here?
This is how I routed all 3 pairs:


This is 4 layers board. L1 and L4 red and blue signal respectively. L2 and L3 will be solid ground planes.
There is a 0.05mm length difference in clock N/P pair but negligible. Also, 0.4 diff between clock pair and data pairs.
Any feedback very welcome
Thanks!

 

you say nothing to worry about right?

I didn't say that. I said I'd buy you a beer if it adversely effected proper operation.

That beer would be cheap compared to your cost if it did make a difference.

Not an expert on 1.5Ghz then how can you advise here?

At least I disclaimed my limited expertise. You're asking questions on the internet: believe nothing, verify everything.

Especially when beer and high speeds are involved.

 

Putting those GND vias will have no effect if you already have a ground plane. At 1.5GHz you need to consider those tracks as a transmission line and ensure impedance matching else you will potentially have EMI/EMC issues. The width and spacing of the traces are important. What chip is that feeding?

 

Putting those GND vias will have no effect if you already have a ground plane. At 1.5GHz you need to consider those tracks as a transmission line and ensure impedance matching else you will potentially have EMI/EMC issues. The width and spacing of the traces are important. What chip is that feeding?

The GND vias are there to provide the return path in the nearby via. Sure, I will have ground reference planes below or above the the signal traces but this is lost in via - hence I added ground vias.
As for impedance matching - yes I will do my best to match them using proper spacing and geometry. However my concern here is the middle, clock signal,which is not symmetrical on one end, doesn't travel in par, and this is all because I had to "untangle" it. I wonder if that alone can break that signal.
The chip is esp32p4.

 

I don't think it'll be a problem. Each via adds a small inductance in series with the track's native inductance and that will change the characteristic impedance but with 2 vias it'll be close to symmetrical. Sometimes its suggested to stitch several small vias in a row rather than a big one.

This site might be helpful: https://www.protoexpress.com/tools/via-impedance-calculator/

 

I use zero Ohm SMT resistors as jumpers for cases like that.

 

I use zero Ohm SMT resistors as jumpers for cases like that.

That works too, but he still needs the vias to swap planes from back to front...

 

Without seeing more of the PCB it is difficult to verify that my suggestion will work.
This is a classic case of the TS deciding that there is only one possible way to solve the problem, and that the only place for any fix is right there, which unfortunately does not seem to work.

Show us an inch or two surrounding that problem area, please.
AND, I seem to have missed the part about the circuit working at 1.5 GHz.

 

I use zero Ohm SMT resistors as jumpers for cases like that.

not at at 1.5 Ghz

 

you mention changing the components side or orrientation
if the other lines that would be swaped in this case are slower, id look at streightening the clock out .

 

In PCB layouts I OFTEN use components to pass over other conductors.

 

In PCB layouts I OFTEN use components to pass over other conductors.

At 1.5 GHz that the op wants ?
How do you match impedance ?
Can you share a trace of the loss over the frequency range .

 

At 1.5 GHz, I would be more concerned about maintaining symmetry through the transition than the simple fact that the pair crosses. If both traces experience similar via structures and reference planes remain continuous, the impact is often much smaller than people initially expect.

Adding nearby ground vias can help provide a cleaner return-current path through the transition and may reduce discontinuities. If possible, I'd also check the differential impedance through the crossover region with a field solver or SI simulation.

There are some good differential pair routing discussions that cover symmetry, skew, impedance control, and via transitions in more detail. This guide might help: https://www.pcbway.com/blog/Engineering_Technical/Best_High_Speed_PCB_Design_Practices_06ad7b8a.html

For a 1.5 GHz signal, I'd mainly focus on keeping the two traces electrically similar and ensuring the reference plane remains intact through the crossover region.