Dear readers,
Above is taken from here . Can anyone recommend transistor Q1 (npn) and Q2 (pnp) to me for driving a mosfet at a 100kHz or higher. What are some of the common best fast switching Q1 and Q2 that can handle high current and high frequency PWM at its base ?

Thank you

 

Why not use a gate driver chip?

Bob

 

What are some of the common best fast switching Q1 and Q2 that can handle high current and high frequency PWM at its base ?

Since the transistors are being using as emitter followers and don't saturate, common higher-current switching transistors such as the 2N2222 and 2N2207 will work.
(LTspice simulation below for a 100kHz square-wave).

For the simulation, the MOSFET is one with a fairly high gate charge (240nC) to charge and discharge.
The peak gate current (blue trace) is about 1A.
Note that the input driver for the circuit must have a low impedance since the peak input current (purple trace) is about 60mA (shown with a 100Ω source resistance).
Not shown is needed decoupling capacitors of 100nF in parallel with 10µF from the Q1 collector to ground.

 

Since the transistors are being using as emitter followers and don't saturate, common higher-current switching transistors such as the 2N2222 and 2N2207 will work.
(LTspice simulation below for a 100kHz square-wave).

For the simulation, the MOSFET is one with a fairly high gate charge (240nC) to charge and discharge.
The peak gate current (blue trace) is about 1A.
Note that the input driver for the circuit must have a low impedance since the peak input current (purple trace) is about 60mA (shown with a 100Ω source resistance).
Not shown is needed decoupling capacitors of 100nF in parallel with 10µF from the Q1 collector to ground.

View attachment 256626

Dear sir, thank you for your reply. I am actually using this to drive a mosfet at high frequency. At high frequency, it needs a mosfet gate driver just like this because the gate-source of mosfet has a little capacitance in it. Thank you, sir

 

Why not use a gate driver chip?

Bob

Agreed - A complementary emitter follower will give 0.6V to 4.4V drive from a 5V logic level input. That might not be enough for normal (i.e. not logic-level) MOSFETs. A gate driver IC will give more output voltage.

 

Hi sir, if my source have a 1000Ohm internal Resistance, the voltage at the gate of mosfet will have this slope. May I know if there is any modification that can address this issue so that the mosfet (high capacitance) will receive a good square wave (100kHz) at its gate. Thank you

 

Hello,

@MrsssSu , You have the bottom transistor connected wrong.
Exchange the collector and emittor and try again.
See the schematic that @crutschow posted in post #3.

Bertus

 

H

Hello,

@MrsssSu , You have the bottom transistor connected wrong.
Exchange the collector and emittor and try again.
See the schematic that @crutschow posted in post #3.

Bertus

Hi, thank you. It works

 

Since the transistors are being using as emitter followers and don't saturate, common higher-current switching transistors such as the 2N2222 and 2N2207 will work.
(LTspice simulation below for a 100kHz square-wave).

For the simulation, the MOSFET is one with a fairly high gate charge (240nC) to charge and discharge.
The peak gate current (blue trace) is about 1A.
Note that the input driver for the circuit must have a low impedance since the peak input current (purple trace) is about 60mA (shown with a 100Ω source resistance).
Not shown is needed decoupling capacitors of 100nF in parallel with 10µF from the Q1 collector to ground.

View attachment 256626

Hi, I actually able to improve the waveform which has higher slope (higher slew rate) by adding this R10. However, it consumes quite a lot of power unfortunately (1 to 2watts). Are there any modification that can be done for this ? And, looks like it switching loss gets better and better as I add more transistor. Is it because of the transistor gain will increase as I increase the number of transistors ?

 

Hello,

Perhaps the following PDF might interest you.
There is a block with speed-up circuits given:

Bertus

 

...........
However, it consumes quite a lot of power unfortunately (1 to 2watts). Are there any modification that can be done for this ?

Below is the circuit using a common CD4050 CMOS buffer, which uses no significant static power, to provide a low-impedance drive to the transistors.
The six buffers in one IC package can be connected in parallel since their response times are likely fairly well matched.
The simulation calculates the average dynamic power at 100kHz for all six buffers as about 2mW total (not shown).

The simulation shows fast switching for all waveforms.

The actual circuit will also require adequate decoupling capacitors, such as a 100nF ceramic across the CD4050 power and ground, and a 10µF electrolytic from the Q1's collector to Q2's collector.

 

If you want to use only transistors, below is a simulation using two Sziklai Pairs as complementary drivers to reduce the input drive requirement.
Their advantage over a Darlington pair is slightly lower output offset and slightly faster switching.

Even with a 1kΩ source impedance, the waveforms still show clean, fast rise and fall times.

 

If you want to use only transistors, below is a simulation using two Sziklai Pairs as complementary drivers to reduce the input drive requirement.
Their advantage over a Darlington pair is slightly lower output offset and slightly faster switching.

Even with a 1kΩ source impedance, the waveforms still show clean, fast rise and fall times.

View attachment 256776

HI, I really like all your circuit !!! I have actually tried all of them and it really works well.

 

Below is the circuit using a common CD4050 CMOS buffer, which uses no significant static power, to provide a low-impedance drive to the transistors.
The six buffers in one IC package can be connected in parallel since their response times are likely fairly well matched.
The simulation calculates the average dynamic power at 100kHz for all six buffers as about 2mW total (not shown).

The simulation shows fast switching for all waveforms.

The actual circuit will also require adequate decoupling capacitors, such as a 100nF ceramic across the CD4050 power and ground, and a 10µF electrolytic from the Q1's collector to Q2's collector.

View attachment 256753

Hi, if I am using a high speed comparator, just wondering, does the duty cycle affect the slew rate (switching speed) of the IC? For Example, at 50% duty cycle, slew rate(switching speed) should be the same as 10% duty cycle right normally? Because, when I measure the switching speed at 50% duty cycle at output of comparator, it is not really the same at 5% duty cycle which is pretty weird and I think that this is caused my scope's limitations and not the IC itself?

 

If you want to use only transistors, below is a simulation using two Sziklai Pairs as complementary drivers to reduce the input drive requirement.
Their advantage over a Darlington pair is slightly lower output offset and slightly faster switching.

Even with a 1kΩ source impedance, the waveforms still show clean, fast rise and fall times.

View attachment 256776

Hi sir, i tested your circuit in real life. When i use an 8V source (V2), the transistors are fine. However, when i use a 12V (V2 as in your diagram), the Q1 and Q2 transistors get hot. How do i solve this issue? I believe is because of the base emitter voltage being too high until it destroy the junction? Thank you

 

Used ZXGD3006E6. I have a model of this gate driver in my model collection.

 

Hi sir, i tested your circuit in real life. When i use an 8V source (V2), the transistors are fine. However, when i use a 12V (V2 as in your diagram), the Q1 and Q2 transistors get hot. How do i solve this issue? I believe is because of the base emitter voltage being too high until it destroy the junction? Thank you

Try base-emitter resistors on Q1 and Q2 to speed up the turn-off

 

It's not likely related to the transistor switching speeds, since that doesn't affect the power dissipation of the transistors when driving a capacitive load, as the MOSFET gate is.
The driver dissipation is largely a function of the load capacitance and the driving frequency.
What load are you driving and what is the switching frequency?

 

Dear sir, thank you for your reply. I am actually using this to drive a mosfet at high frequency. At high frequency, it needs a mosfet gate driver just like this because the gate-source of mosfet has a little capacitance in it. Thank you, sir

The gate capacitance (charge) should indeed be handled by the driving device. If the original design shows part of an integrated chip driving an external fet, then sure, need a output stage to drive the ext fet.

If the PWM is already coming from some device, then about 99.99% of those devices can easily handle (source and/or sink, assist with pull-up or pull-down, etc) the gate charge, and do it very fast.

You can control low gate capacitance fets with just about any output from just about all devices that have PWM output.

So why not just drive fet gate directly with PWM and use a pull-down resistor (if needed).
Post #12, connect fet gate directly to V1(in) Pulse.

 

It's not likely related to the transistor switching speeds, since that doesn't affect the power dissipation of the transistors when driving a capacitive load, as the MOSFET gate is.
The driver dissipation is largely a function of the load capacitance and the driving frequency.
What load are you driving and what is the switching frequency?

Hi, I am driving it at 15khz square wave (very nice square wave) and even if I leave it driving no load (open-circuit), if I set V1 at 16V square wave with a 12V (V2), transistor (Q1,Q2) get hot. However, when I set V1 at 12V square wave with a 12 V (V2), transistors are fine. My V1 internal resistance is pretty low. Hmm, what could be the reason ? I did not expect that