I am using 32Khz for LSE and 12.288MHz for HSE, so are you saying I don't need to bother with isolated GND planes and guard rail ?

The idea behind the GND island is to prevent return currents from other parts of the circuit flowing underneath the oscillators circuit - inadvertently shifting the GND potential, thus potentially introducing Phase noise and/or frequency shifts. Consider an oscillator circuit an analog circuit with quite low voltages (we measured about 0.3 VSS on some STM32) - thus susceptible to interference. We're calling this setup (guard ring plus the island in the next layer) the "bathtub" for the oscillator.
No need for an island on layer 3. And I'd suggest to have the connection between Island and "global GND" on layer 2.

 

The idea behind the GND island is to prevent return currents from other parts of the circuit flowing underneath the oscillators circuit - inadvertently shifting the GND potential, thus potentially introducing Phase noise and/or frequency shifts. Consider an oscillator circuit an analog circuit with quite low voltages (we measured about 0.3 VSS on some STM32) - thus susceptible to interference. We're calling this setup (guard ring plus the island in the next layer) the "bathtub" for the oscillator.
No need for an island on layer 3. And I'd suggest to have the connection between Island and "global GND" on layer 2.

Thanks du00000001

I have removed the island on layer 3 (Inner Layer 2) and connected th island to the global GND on layer 2 as you suggested.

Does this now look correct ?

 

why is the last screenshot showing inner layer2 (GND) as continuous plane? the whole point is to prevent some random current go near oscillator. and your layout totally allows massive current to flow right through it on inner layer 2.

an island is a land feature completely surrounded by water. then you need add a single bridge from island to the landmass.
in terms of PCB layout that means making single zone (an island) that is completely detached from GND plane, use all layers (top to bottom) or at least the top two (floating island). stitch the perimeter of the island with vias. and finally add the bridge - a single point that connects island to the rest of the GND plane.

this should prevent any interference current from flowing directly though the oscillator.
pick any two points on your board (i called them A and B) and draw straight line though them. that is the path of least resistance on a solid plane. that is what you want to avoid. any such random current must be forced to go around the island. and that means you need to create separation between island and the rest of the GND plane...

that is if you care about resisting and possibly surviving EMP

 

why is the last screenshot showing inner layer2 (GND) as continuous plane? the whole point is to prevent some random current go near oscillator. and your layout totally allows massive current to flow right through it on inner layer 2.

an island is a land feature completely surrounded by water. then you need add a single bridge from island to the landmass.
in terms of PCB layout that means making single zone (an island) that is completely detached from GND plane, use all layers (top to bottom) or at least the top two (floating island). stitch the perimeter of the island with vias. and finally add the bridge - a single point that connects island to the rest of the GND plane.

this should prevent any interference current from flowing directly though the oscillator.
pick any two points on your board (i called them A and B) and draw straight line though them. that is the path of least resistance on a solid plane. that is what you want to avoid. any such random current must be forced to go around the island. and that means you need to create separation between island and the rest of the GND plane...

that is if you care about resisting and possibly surviving EMP

View attachment 363327

@panic mode
Inner layer 3 could be continuous as inner layer 2 ist shielding the oscillator circuit sufficiently - provided the guard ring vias do not connect layers 2 and 3.

@freeflyer
Either use blind vias connecting the guard ring only to the layer 2 GND island (would be my preferred solution - that's how my colleagues and I implement such oscillator circuits) OR make sure the guard ring vias do not connect to GND on layers 3 and 4 (e.g. by exempting the via areas on lyers 3 and 4 from flooding).

The trace between the layer 2 island and the global GND on this layer is looking fine. And 0.5 mm trace width should really suffice as the current should be minimal (although not zero).

 

Thanks du00000001 and panic mode

Inner layer2 (GND) was changed to a continuous plane as suggested by du00000001

But is there any benefit into changing inner layer2 from an isolated island to an continuous plane ?

There are no signals running under the crystals, so I don't gain anything by making inner layer 2 a continuous plane.

And don't blind vias increase manufacturing costs ?

In which case I might as well use an isolated island on inner layer 2 as well as inner layer 1 as shown below...

 

Inner layer 3 could be continuous as inner layer 2 ist shielding the oscillator circuit sufficiently - provided the guard ring vias do not connect layers 2 and 3.

no objection from me, i was building many projects (including 1 layer) without any ground planes and they all turned out alright even when placed near large inverters.

but i am trying to keep an open mind, maybe this is for a different application. perhaps it will be part of some missile control and target of intentional and focused interference.

There are no signals running under the crystals,

no signals that you can see or think of... but... not all signals are the ones you create. every piece of metal is an antenna and picks up noise. that includes every PCB track, plane, island... they start resonating when exposed to right frequencies.

it is like house of cards. it is relatively easily easily protected in a calm room. not so easy when built on a deck of boat - specially if weather is bad.

And don't blind vias increase manufacturing costs ?

yes they do.

 

Thanks panic mode

I am just trying to follow recommend guide lines and minimise potential EMI risks

The original board I designed used an analogue audio amplifier, but due to poor layout there was hiss and clicks.

It's not cheap to get a board fabricated and assembled, so I am being extra careful to minimise EMI

And if this ever goes into production, it might need to pass EMC tests

In this case the recommended guidelines ST provide for the crystal layout is not clear, but once understood it should be easy enough to implement ?

The board is compact and fitted with buck-boost converters, a class D amplifier (PWM) and a bluetooth receiver so this could be an on board source of EMI

I didn't have problems with the crystal on the original board, which had no isolated planes or guardrails. Although I only used the 32kHz LSE crystal (I didn't use the HSE crystal).

So I'm in two minds whether or not to use isolated planes with guard rails and Im trying to understand the risk.

Is there a risk that using isolated planes with guard rails might not work and I would be better off using my original design ?

 

The original board I designed used an analogue audio amplifier, but due to poor layout there was hiss and clicks.

assuming audio amplifier was driving speaker and that is how you could hear the hiss and clicks.

but.. that is not what you are asking for in this thread... you created thread with another XY problem.


your MCU is not a victim here, victim suffering from interference is the amplifier and the likely source of mentioned interference is the MCU or peripherals driven by it.

 

assuming audio amplifier was driving speaker and that is how you could hear the hiss and clicks.

but.. that is not what you are asking for in this thread... you created thread with another XY problem.


your MCU is not a victim here, victim suffering from interference is the amplifier and the likely source of mentioned interference is the MCU or peripherals driven by it.

yes thats correct, I was just explaining why I am taking extra care and effort with the layout this time to mitigate EMI risks (such as following layout guidelines for the crystal).

amd in the event this design could be a pre-production prototype and could be EMC tested

so is my latest layout now correct ?

 

i see no problem with it. it is a PCB version of Faraday's Cage and it is connected to main GND at one point. can't do much better than that.

the single point of connection is also used everywhere where one is combating noise and interference. that includes audio circuits, analog and digital stages, drivers and feedback etc. one of the key objectives here is that reference node of each of those circuits meet at a single point (no continuous plane).

you can see that everywhere... PSU, amps, motor drivers, DAQ, you name it...!
principles are the same but there are infinite number of designs and ways to implement them.

so why don't you show problem design?

 

i see no problem with it. it is a PCB version of Faraday's Cage and it is connected to main GND at one point. can't do much better than that.

the single point of connection is also used everywhere where one is combating noise and interference. that includes audio circuits, analog and digital stages, drivers and feedback etc. one of the key objectives here is that reference node of each of those circuits meet at a single point (no continuous plane).

you can see that everywhere... PSU, amps, motor drivers, DAQ, you name it...!
principles are the same but there are infinite number of designs and ways to implement them.

so why don't you show problem design?

Thanks,

Below is the crystal layout on the original board, there are no isolated planes, no guard rail and some tracks are routed underneath.




Before redesigning the PCB, I did this PCB design course aimed at designing for EMC...

https://www.skool.com/pcb-design-mastery-9530/about

Some points I took away from the course were:

1. to use GND on both inner layers
2. ensure tracks have a solid return reference plane underneath
3. add a GND via when changing between layers

So I have implemented this for high speed signals to maintain signal integrity, reduce cross talk, reduce radiated and conducted emissions.

What problem design are you referring to ? Do you mean the audio interference I had on the original design ?

If so, I wrote a post last year about that problem (see link below). However, I have since changed the amplifier.

I previously used a class AB amplifier with an analogue interface. I am now using a class D amplifier with a digital interface (I2S) so don't have the same problem anymore. Class D is also more efficient, which is critical for this small battery powered device.

https://forum.allaboutcircuits.com/...io-amplifier-even-from-a-flashing-led.207828/

 

i am talking about PCB that you made previously - one with analog audio amp that was exhibiting hissing and clicking.

 

Tackle one problem at a time. Crystal oscillator PCB layout might have nothing to do with audio amplifier clicks and hiss.
What you have is a "mixed signal" application, mixing analog and digital in the same project. This calls for another set of stringent PCB design rules.

 

i am talking about PCB that you made previously - one with analog audio amp that was exhibiting hissing and clicking.

Yes thats explained in the link...

https://forum.allaboutcircuits.com/...io-amplifier-even-from-a-flashing-led.207828/

But its not longer relevant because I am using a different amplifier

 

Tackle one problem at a time. Crystal oscillator PCB layout might have nothing to do with audio amplifier clicks and hiss.
What you have is a "mixed signal" application, mixing analog and digital in the same project. This calls for another set of stringent PCB design rules.

The issue I had with the amp is no longer relevant because I am using a different amplifier, I was just using it as an example as to why I am taking extra care with the crystal layout.

The crystal layout has nothing to do with the issue I had with the amp. But its made me more cautious, so I am making more care to use best practices to minimize EMI.

I dont want to pay £200 for a new board, only to find it has other EMI issues.

And if it goes into production it might need to pass EMC tests.

So Im just taking extra care with the layout this time.

And ST provide the application note with guidelines for the crystal PCB layout.

 

Crystal oscillator PCB layout guidelines are relevant to oscillator stability, not for EMI issues.
For EMC tests, you have to examine the entire PCB, not just the crystal oscillator.

 

This fancy guard ring plus the GND island underneath surrounding the original analog input line to the amplifier (Island connected to global GND close to the amplifier's input) would most likely have prevented the trouble with hissing and alike. ("Most likely" because analog circuits are also susceptible to supply voltage noise. So add "make the analog supply voltage stable" (and maybe add a filter ro prevent noise created by the digital parts of your device entering the analog section.
And OK - using a D-class amplifier with a digital input is a valid solution to minimize such effects. Although it might be somewhat more expensive than the analog variant.

BTW: I once had fancy crosstalk from an address bus to the analog signal prior the end amplifier. That was just V0.9 and the space was more than constrained. Anyway - had I ever had to do the redesign I would have simply added the guard ring and the shield island underneath

 

For STM32 crystal layout, isolated planes are optional. Short, symmetric traces matter most. Keep crystals and load capacitors close to MCU pins. Avoid running digital signals nearby. A solid, continuous ground under the oscillator works well. Guard rings or isolated islands can help reduce noise. But they aren’t required for most boards. Make sure VSSA and VSS are tied properly at the MCU. Excessive splits or floating islands may cause parasitic capacitance issues. Your previous layouts likely work fine without these additions. If you want practical guidance, check this article on oscillator troubleshooting. Community discussions confirm this approach, especially for 4-layer boards. See this Reddit thread about using guard rings and isolated planes. Focus on low parasitic capacitance, good grounding, and minimal interference.

 

Good. But The all copper under the Crystals will be removed including top layer, Inner layers and bottom layer. Thank you.

 

Definitely lots of conflicting advice here, but I'll add my thoughts anyway (as an in-house EMC consultant):

• I'd ignore the datasheet recommendations, and not split grounds. Solid ground plane on layers 2 and 3, the entire size of the PCB. There are no advantages to splitting ground in this situation; you're just making the design more complicated and introducing the risk of resonant structures.
• As others have suggested I'd keep the traces to the crystals short, and try and separate the two crystals as much as practical. I think you've done a good job of this already.
• Layer 1 flooded ground / guard trace is optional and not particularly important (compared to the physical location of the two crystals). You can have it, but you must not have bits of ground that aren't tied to the ground plane with vias. I think you've done a good job of this as well.
• At least 1 ground via for every ground pad - no exceptions. You don't want two capacitors sharing a ground via.

A good video on this subject:

Overall, I think if you take the design as it is in post #22, remove the split ground (solid ground plane on layers 2 and 3), and add back in the vias you had for every capacitor pin, you will be golden.