For those questioning the sense guard ring/GND island:
https://www.st.com/resource/en/appl...als-and-stm32-mcusmpus-stmicroelectronics.pdf
Layout recommendations are p.45 ff. In the times of crystal metal cans it was even wise to ground the can (yes - they are easily solderable!).

 

For those questioning the sense guard ring/GND island:
https://www.st.com/resource/en/appl...als-and-stm32-mcusmpus-stmicroelectronics.pdf
Layout recommendations are p.45 ff. In the times of crystal metal cans it was even wise to ground the can (yes - they are easily solderable!).

Unfortunately guidance in datasheets / app notes is often incorrect. Such advice is copied over and over again, dating back decades without any review.

The idea of splitting grounds to "reduce interference" dates back to the days of the very first PCBs, with mostly analogue or low speed digital circuits. It has long been superseded by the advice to use a solid, continuous reference plane to provide a low impedance return path at high frequencies.

In general I'd always take datasheet advice with a very large pinch of salt, and take a "trust but verify" approach. When looking for up-to-date, correct advice I always go looking for the opinion of multiple EMC consultants (Keith Armstrong, Rick Hartley, Ralph Morrison etc.), who always explain why they recommend what they do.

 

Definitely lots of conflicting advice here, but I'll add my thoughts anyway (as an in-house EMC consultant):

You hit the nail on the head, there is lots of conflicting advice which may be the reason why EMI is considered a "black art".

I even got conflicting advice on the STM32 forum...

https://community.st.com/t5/stm32-m...tor-separated-gnd-plane-confusion/td-p/875511

So because of this, I am considering doing away with the guard rail and isolated grounds.

There seems to be a risk that the guard rail and isolated grounds could make things worse if not done correctly so I may as well just use the same design I used before.

Below is the current design...










I have positioned the components as MCU -> crystal -> load capacitors.

Whereas previously I positioned the components as MCU -> load capacitors -> crystal .

Does the order of the crystals and load capacitors matter ?

 

"Done correctly" is always a precondition.
Although my colleagues consider me an EMC Pro I'm not offering consulting. Just discussing with other pros.
I cannot recall how often I've implemented this concept - even on 2-layer PCBs. Never had issues with this.
But do what you want.

 

I am designing a 4 layer PCB which uses an STM32L433 and working on the layout for the LSE and HSE crystals.

I referred to the application note AN2867 for guidance, but I am confused by the isolated ground plane underneath the crystals as shown in Figure 14...

View attachment 363076

https://www.st.com/resource/en/appl...als-and-stm32-mcusmpus-stmicroelectronics.pdf

The layout is shown in the screenshots below and include:

1. Isolated plane under the crystals on inner layer 1 and 2
   1. Note that both inner layer 1 and 2 are ground planes
      1. Inner layer 1 is continuous ground plane
      2. Inner layer 2 has some power tracks within the ground plane
2. Connected isolated ground plane to pin 12 (GND) of STM32
   1. Pin 12 is VSSA (analogue ground), will this be a problem ?
   2. The STM32L433 only has a single ground pin (18)
3. No tracks run under the crystals

View attachment 363077


View attachment 363078


View attachment 363079

View attachment 363080

View attachment 363081

I have designed a few boards using this STM32 device and did not use isolated planes under the crystals or a guard rail, but it still worked. Even the ST Nucleo development board for this MCU does not use a guard rail.

So should I continue with these isolated planes and guard rail or is there a risk it could cause issues ?

I dont know whether I should just design it the way I have previously, I would be furious if I spent a few hundred pounds on PCB fabrication and assembly only to find out that the crystals don't work due to the isolated planes and guard rail.

But the guidelines recommend this layout, so I am trying to do it correctly especially if it helps with EMI.

Below is an example how I previously designed the layout for the crystals....


View attachment 363083

I have to start with owning that I am not familiar with that particular STM32. I am familiar with ST documentation though and best practices w.r.t EMI as well as digital and analogue design.
Generally, ST will produce EMI performance graphs for their uC parts so if they do that for this uC then you may be best to follow their guidelines as closely as possible (if not take that part of the layout, trackwork and via placements verbatim).
More typical for good EMI performance though is to never ever split a ground plane. Think of it this way; if you split the ground plane and successfully block a current in that ground plane from taking the path it wants to take without the split then you are forcing that current to take a longer path to get where it wants to go. By definition then, you have created an area of EM radiation as the current flows around the new path. And that is not good.
If the issue is noise getting into the oscillator circuits causing jitter then the answer should only ever be to keep strong unrelated signals away from that area. You should also try to avoid encouraging currents to flow under the area. Keep in mind that a DC current will return by the most direct path possible but high frequency return currents will tend to flow directly beneath the trace with the high frequency signal. Any other path incurs higher inductance which tends to act against the flow of current.
The conflict between the st advice and mine I cannot resolve I am sorry. There may be other considerations with the ground pins of the uC. Actually, if there are only two GND pins and one of them is supposed to be connected to this isolated ground plane, that is a red flag for EMI. If I understand that correctly then the chip itself becomes part of the EMI radiator.
You need to think carefully about the currents that may flow and where those currents flow.
I wish I could be more definitive.
Good luck.

 

You hit the nail on the head, there is lots of conflicting advice which may be the reason why EMI is considered a "black art".

I even got conflicting advice on the STM32 forum...

https://community.st.com/t5/stm32-m...tor-separated-gnd-plane-confusion/td-p/875511

So because of this, I am considering doing away with the guard rail and isolated grounds.

There seems to be a risk that the guard rail and isolated grounds could make things worse if not done correctly so I may as well just use the same design I used before...

I have positioned the components as MCU -> crystal -> load capacitors.

Whereas previously I positioned the components as MCU -> load capacitors -> crystal .

Does the order of the crystals and load capacitors matter ?

So you have done a total U-turn and reverted to your original layout.

I refer your to my initial statements:
1) Keep all traces short and straight and close to the MCU.
2) Keep the capacitors close to the crystal.
3) Connect the capacitors to the ground plane.

As to the order of the components in the layout, I think that it does not matter if you adhere to the three rules above.
I would put the crystal first, closest to the MCU.

 

You hit the nail on the head, there is lots of conflicting advice which may be the reason why EMI is considered a "black art".

I even got conflicting advice on the STM32 forum...

https://community.st.com/t5/stm32-m...tor-separated-gnd-plane-confusion/td-p/875511

So because of this, I am considering doing away with the guard rail and isolated grounds.

There seems to be a risk that the guard rail and isolated grounds could make things worse if not done correctly so I may as well just use the same design I used before.

Below is the current design...


View attachment 363403


View attachment 363404

View attachment 363405


I have positioned the components as MCU -> crystal -> load capacitors.

Whereas previously I positioned the components as MCU -> load capacitors -> crystal .

Does the order of the crystals and load capacitors matter ?

Keeping the traces short is critical and the higher the frequency the more critical it is. There is no series resistor so I assume the frequency is not crazy high and not an overtone crystal. So the order should not be all that critical. Having said that I generally prefer to put the caps on the far side of the crystal for the following reasons;
1. the crystal is the inductive component in that circuit so it is more likely ti have higher voltages and a physical structure more adept at radiating. The caps on the far side might keep this situation under better control. I did say my reasoning would be dubious.
2. the oscillator and uC would physically more difficult to hand solder the caps and to inspect the soldering on the caps even if they are auto placed and reflowed.
I think these are ignoble points for any other reason.
Somewhere else I saw advice that you should share a via on the caps. Do not do this. Look up the inductance of a via. That is the worst advice I have heard on here in a long time.
As I said before, keep the currents in mind. Where they flow and what they flow through.

 

Unfortunately guidance in datasheets / app notes is often incorrect. Such advice is copied over and over again, dating back decades without any review.

The idea of splitting grounds to "reduce interference" dates back to the days of the very first PCBs, with mostly analogue or low speed digital circuits. It has long been superseded by the advice to use a solid, continuous reference plane to provide a low impedance return path at high frequencies.

In general I'd always take datasheet advice with a very large pinch of salt, and take a "trust but verify" approach. When looking for up-to-date, correct advice I always go looking for the opinion of multiple EMC consultants (Keith Armstrong, Rick Hartley, Ralph Morrison etc.), who always explain why they recommend what they do.

For a multi layer pcb I always have at least one ground plane strategically placed and when all the routing is in place I pour ground connected copper on all other layers and stitch them all together with stitching vias. This process can take a while. You need to be careful you are not creating antennas anywhere.

 

Thanks for everyone who took the time to comment, its appreciated.

It was only due to conlficting advice that I decided to do away with the guard rail and isolated planes.

Then I thought of an alternative solution.... if anyone would like to take the time to modify the layout, I have attached the Kicad files with just the processor, crystal and capacitors.

See image below and attached zip file...

 

This is your project and your outcomes and this is how we learn. Good luck.