Hi,

I try to layout three differential pairs in a close proximity. This is my initial plan:


The main concern I have is the proximity of the middle differential pair and the upper one. The middle one goes on the other layer(blue trace). Is this viable layout?

Next thing is the impedance calculations. Kicad 9 that I use provides a calculator that with two options Analyze and Synthesize. Once I input 90 Ohms there and synthesized, it stays, but how can I make sure all three pairs indeed have this 90 Ohms?

Thanks!

 

One of the reasons for using differential pairs is for maintaining signal integrity. In order to achieve this, you want traces to be as straight and short as possible.

I would choose short traces over worrying about proximity. Instead of 45° traces, use smooth curves.

The blue traces can be shorter by moving the vias on the left side on to a more direct path.

 

good start
differential lines are normaly over a ground or power plane . do you have one ?
what is the frequency of the signals ?
you wpuld normal have to ensure the p and n of the signal are the same length , possibly by introducing snacking on one trace or the other.
also there might be a requirment to keep the multiple pairs the same length.
up by J2, the diff pair looks close to the other single ended trace ,

it does look like the lower red pair move apart near j1, this woukd change impedance .

as you see by the possibke need to match lengths by adding wigles, you dont need to keep traces short or streight, but dpimg so makes signal integrity easier.

if youve not seen it , I find this a good referance
https://www.ti.com/lit/pdf/spraar7

 

I would choose short traces over worrying about proximity. Instead of 45° traces, use smooth curves.

Easy to say hard to accomplish when there are 3 pairs of high speed differential in such a short proximity.

drjohsmith, thanks a lot for your response. The document you referenced is great.

differential lines are normaly over a ground or power plane . do you have one ?

I do have ground planes but the problem is I have a voltage regulator right below the differential pair, on bottom layer. This is because I also do care about having the signal voltages stable and as close to the pin as possible. I think it should not particularly hurt the differential on the upper layer.
This is how it looks now:
Top layer:


Bottom layer:

what is the frequency of the signals ?

The freq of all 3 differential pairs is 100-150Mhz

also there might be a requirment to keep the multiple pairs the same length.

So do I absolutely need to make them the same length, even if that requires "snaky" tracing? What about signal reflection in that snaky area?

Also, as I mentioned in my very first post. how can I ensure the 100 ohm impedance of each pair? I read this is a strong requirement.

Thanks!

 

Easy to say hard to accomplish when there are 3 pairs of high speed differential in such a short proximity.

drjohsmith, thanks a lot for your response. The document you referenced is great.


I do have ground planes but the problem is I have a voltage regulator right below the differential pair, on bottom layer. This is because I also do care about having the signal voltages stable and as close to the pin as possible. I think it should not particularly hurt the differential on the upper layer.
This is how it looks now:
Top layer:
View attachment 363191

Bottom layer:
View attachment 363192

The freq of all 3 differential pairs is 100-150Mhz


So do I absolutely need to make them the same length, even if that requires "snaky" tracing? What about signal reflection in that snaky area?

Also, as I mentioned in my very first post. how can I ensure the 100 ohm impedance of each pair? I read this is a strong requirement.

Thanks!

so frequency is critical decision,
Id worry if they were Ghz , putting curves not 45 degrees, balanced via placment etc .

Id worry if they were analog,

but if they are digital, say LVDS , then not so much.

Id still be matching the lengths of the p / n pair so same length in a pair , and check your requirments, do the pairs need to be length matched.

Is this a 2 layer board ? are those LDO reguoators ? how hot are the ldo going to get ?

snaking , between a p / n pair , absolutely nesicery.
two points ,
over simplified, the wave form has to travel down between the pair, if one of the pair is longer than the other, the wave gets stretched, impedance changes !
also at the receiver, it works by extracting the difference in voltage, ignoring any common voltage, such as nouse. If say p side arrives 500ps befor the n side due to different length lines, then for that 500ps, you get what ?

Again, 150 Mhz , much lower worry than say 3 Ghz, but principle is same.

just re voltage stable, great thought, but enginerring is about comoramises.

The ldo are relatively slow to respond to power spikes , say 1 us, where as spikes are ns . what you do is put low impedance / ceramic capacitors on the pins of the connector, these take care of the ns glitches.
the ldo then can be a few cm away or even more without degrading volages on the connectors , alowing placment away from critical signals which should be routed first. moving the ldo also allows more copper on them to allow more heat disipation.

 

I would do it something like this:

 

Thanks, a lot of good points.
In the layout @MrAl proposed above, the two differential pairs are crossing each other on two layer, meaning one is right below the other. The EMI of one may affect the other, not good right? Also, the rule of thumb is the two signals should be 5xWidth from the other pair, while @MrAl layout the two upper pairs are around 2xtrace_width from each other on the J1 side.

 

Thanks, a lot of good points.
In the layout @MrAl proposed above, the two differential pairs are crossing each other on two layer, meaning one is right below the other. The EMI of one may affect the other, not good right? Also, the rule of thumb is the two signals should be 5xWidth from the other pair, while @MrAl layout the two upper pairs are around 2xtrace_width from each other on the J1 side.

we did ask, do you have a ground plane,
if so the top can not interfear with the bottom.

as for rules,
you have to be pragmatic,
its engineering .
another rule is not to have vias , but you need to ,
the rule about wires crossing, if you dont have plane between ,
you look at coupling. this is proportional to the length of tracks in parallel, frequency , and distance. as the wires are at near enough 90 degrees , distance is next to zero, and frequency low, so little coupling , not to worry.
distance between pairs , can be less than for single ended signals, again tracks are short , so little real worries.

advantage is tracks are much closer to same lengths, and fewer / less sharp bends.

 

Here is an improvement. There is reduced coupling between the red and blue traces.

 

Here is an improvement. There is reduced coupling between the red and blue traces.

View attachment 363211

im wondering what plugs into j1 and j2 ?
bet is its something like mPCIe ?

 

As drjonsmith mentioned: separate GND-planes are absolutely necessary for a proper design of impedance matched transmission lines. You can't do that wit a simple 2-layer board. 4 layers are absolutetly necessary for a proper return path to GND of the individual p/n-signals. The p-signal doesn't return as the n-signal but each signal returns individually through the GND-plane in layer 2 and 3. With a 4-layer board you need not worry about crosstalk between signals on the top and bottom layer.

Up to now we do not know the frequency of your differential signals. Is it USB, mPCIe or what else? Depending on that different requirements exist for trace length matching, even between 2 different signal pairs. Meandering a single line of a pair is the state of the art technique for length matching. As long as you are working with digital signals in the range of some 100 MHz, you can use a bend in your signal line (usually 45°) and you should use a chamfer at the bend.

Usually the pins of an IC or a connector don't have the coŕrect distance for your required impedence. Therefore you should connect them in the shortest possible way to the correct line spacing, usually with a symmetrical angle of 45°.

 

Thanks, a lot of good points.
In the layout @MrAl proposed above, the two differential pairs are crossing each other on two layer, meaning one is right below the other. The EMI of one may affect the other, not good right? Also, the rule of thumb is the two signals should be 5xWidth from the other pair, while @MrAl layout the two upper pairs are around 2xtrace_width from each other on the J1 side.

Hi,

You mentioned me in this reply but I don't see any reply from me in this thread

 

im wondering what plugs into j1 and j2 ?
bet is its something like mPCIe ?

It is a connection between a camera sensor and a microcontroller.

Up to now we do not know the frequency of your differential signals. Is it USB, mPCIe or what else?

I think I mentioned this in my previous post, the frequency will range between 100-150Mhz (depending on selected data fromat)
This is camera sensor connector utilizing MIPI CSI 2 interface.

You can't do that wit a simple 2-layer board. 4 layers are absolutetly necessary for a proper return path to GND of the individual p/n-signals.

This is interesting, why 2 layers won't be suficient? Isn't jumping between layers with a high speed differential pair highly dicouraged? Also what do you mean by each diff pair needs a return path to GND? They will all be surrounded by ground planes.

The p-signal doesn't return as the n-signal but each signal returns individually through the GND-plane in layer 2 and 3.

I don't get it all all, why do you say they return individually? Why separate planes for each of them? Cany you mention a reference where did you learn this from? Thanks.

You mentioned me in this reply but I don't see any reply from me in this thread

Yep, my bad, sorry. I meant MrChips who draw his suggested layout. Thanks @MrChips

 

Yep, my bad, sorry. I meant MrChips who draw his suggested layout. Thanks @MrChips

Hi,

No problem, I just thought for a minute that maybe it was in another thread or something.

One thing I can add though...

Traces that run perpendicular to each other should have less crosstalk. The Neumann integral kernel for mutual inductance Lm contains the dot product between the two elements:
Km=(dL1*dL2)/r
where the asterisk is the dot product. The total mutual inductance Lm would be a sum of those Km, but because a property of the dot product involves direction, when the direction is perpendicular Km is always zero, so the sum is zero. Anything other than 90 degrees there will be a coupling, but for each current filament the Km is zero. In trig terms, Km=|dL1|*|dL2|*cos(angle), and angle=90 degrees so Km=0.
So the inductive coupling would be zero except for small imperfections, but then it's a matter of how that small nonzero coupling compares to the other inductances and so it would be a small effect. It's always relative though of course.

The capacitive coupling is a little different, but because the area where they cross is so small, that becomes very small also. For two traces that cross at 90 degrees on either side of maybe an FR-4 pc board, we might see less than 1pf of mutual capacitance. That is very small compared to other imperfections.
Cm would be roughly equal to e0*er*w^2/d where w is the width of each trace and d is the distance between them. This could work out to e0/4 for example. Again, this is relative as well.

 

Don't over think things @mondo90
If your signal really is only 150 MHz , and the connectors are only a few 10 of mm apart , it's going to work .
But I have suspicion MIPI might be faster than that. Check
4 layers is a good choice .
The extra cost increase or time to delivery of 4 over 2 is minimal.. only significant if your making thosands of , or making them yourself.
4 layeres allow a good solid ground and power , which if it goes wrong , is one of the hardest things to diagnose. It's so random .
It also allows good area to dissipate heat from those LDO.

As you can tell from the answers.
The details of how any micro strip / stripline works is actuly very well understood in mathematics and physics .
They are the backbone of most boards
The engineering chalange , is to know when to apply what level of design .
If it was say a 300mm long line , running at say 100 GB/s , or if it was many hundred of lines in a GHz ddr4 interface , or just a single track going 2 mm between chops at 1Gb/s , these are all potentially impedance controlled situations , but I'd apply totally different rules for each.
The hard part you have , is trying to learn what matters.
The forums is well staffed with very intelligent people , who can tell you down to the atomic level how things work , if you want .
But for this case , I'd not worry , just keep the tracks short , balanced in length and above a ground plane. Ensure if you have two planes , they are linked in many places , if one power one ground , decoupling capacitors ..

 

Hello again,

Oh so the intended frequency is around 150MHz?

In that case, for two traces 0.05 inches wide that cross perpendicular to each other on an FR-4 PC board would couple capacitively with approximate impedance:
Z=-30000*j

which if it was just a resistor it would be around 30k Ohms. It's not a resistor, but it's still pretty high. The actual coupling would depend on the other impedances too such as the driving impedance and the load impedance.

The impedance goes down as the square of the ratio of the trace width to that 0.05 inches. So for traces that are 0.1 inches wide, since that is an increase of 2 times, the impedance would go down by a factor of 4. If the traces were thinner by a factor of 2 ( both 0.025 inches in width) then it would go up by a factor of 4.

 

Thanks you all for all the suggestions. I am currently going through some reading as I need to level up my transmission lines knowledge..

Oh so the intended frequency is around 150MHz?

Unfortunately @drjohsmith was right with his feeling it may be higher.. my initial 150 mhz statement was me stupidity following AI (gemini) answer to what the frequency of the CSI MIPI would be for my configuration. Turns out it gave me the pixel clock speed instead of the actual frequency of ~1Ghz

Now, in light of that I think I need to be super careful with my layout.

 

Thanks you all for all the suggestions. I am currently going through some reading as I need to level up my transmission lines knowledge..


Unfortunately @drjohsmith was right with his feeling it may be higher.. my initial 150 mhz statement was me stupidity following AI (gemini) answer to what the frequency of the CSI MIPI would be for my configuration. Turns out it gave me the pixel clock speed instead of the actual frequency of ~1Ghz

Now, in light of that I think I need to be super careful with my layout.

Ghz
you should be looking at 4 layeres,
definately balancing lengths,

 

Thanks you all for all the suggestions. I am currently going through some reading as I need to level up my transmission lines knowledge..


Unfortunately @drjohsmith was right with his feeling it may be higher.. my initial 150 mhz statement was me stupidity following AI (gemini) answer to what the frequency of the CSI MIPI would be for my configuration. Turns out it gave me the pixel clock speed instead of the actual frequency of ~1Ghz

Now, in light of that I think I need to be super careful with my layout.

Hi,

Oh ok, well then that brings us down to about:
Z=-4500*j

Frequency is in the denominator, so if you double the frequency you halve the impedance, and if you halve the frequency you double the impedance.
At 500MHz that would mean Z=-9000*j approximately.
This is for a double sided FR-4 if you add layers it would get more complicated because you might have traces on a third copper layer.

Since that basic formula neglects the fringing part of the field, we might see a 40 percent increase in actual capacitance. This leads to an impedance that would be around 70 percent of that above or around:
Z=-3150*j

You can think about that kind of coupling to start with. If this involves the output of a logic gate, it may not be significant, but testing is always a good idea. 0.050pf to 0.065pf isn't that much capacitance but I guess you never know how this compares to the other values on the board and other proximities.

 

Hi,

Oh ok, well then that brings us down to about:
Z=-4500*j

Frequency is in the denominator, so if you double the frequency you halve the impedance, and if you halve the frequency you double the impedance.
At 500MHz that would mean Z=-9000*j approximately.
This is for a double sided FR-4 if you add layers it would get more complicated because you might have traces on a third copper layer.

Since that basic formula neglects the fringing part of the field, we might see a 40 percent increase in actual capacitance. This leads to an impedance that would be around 70 percent of that above or around:
Z=-3150*j

You can think about that kind of coupling to start with. If this involves the output of a logic gate, it may not be significant, but testing is always a good idea. 0.05pf isn't that much capacitance but I guess you never know how this compares to the other values on the board and other proximities.

can I check your talking about the diff pairs that cross at 90 degrees to each other ?

standard board, thats 1.6mm thick, in a 100 ohm differential pair ,
are we looking at micro strip or strip line now ?