Can you pls take a look at it?!

What is the file format? The preference is for materials to be posted on this site to prevent future viewers from finding broken links and being taken to untrustworthy sites.

 

What is the file format? The preference is for materials to be posted on this site to prevent future viewers from finding broken links and being taken to untrustworthy sites.
View attachment 213020

It's a (.pdsprj) file, and i tried to attach it to my post but looks like it's an invalid format here

EDIT: look...

 

It's a (.pdsprj) file, and i tried to attach it to my post but looks like it's an invalid format here

EDIT: look...

You dont get any display on the LED because you're using the wrong type of 7-segment LED. Choose Common Anode type instead because the outputs of 7447 are "active low".

The CA 7-segment should have the common pin point up. See my schematic to get some clue.

Allen

 

You dont get any display on the LED because you're using the wrong type of 7-segment LED. Choose Common Anode type instead because the outputs of 7447 are "active low".

The CA 7-segment should have the common pin point up. See my schematic to get some clue.

Allen

Tnx Allen
After my last reply, i double checked and found the problem and i solved it...
It was as you said and i didn't know about 7447 output active state.

 

announcement:
Both projects are now working.
special thanks to @dl324

 

Both projects are now working.
special thanks to @dl324

I didn't do much of anything and I still don't think that's what your teacher intended for either project.

There's little learning if you use a 4 bit adder IC instead of designing and cascading a 1 bit adder.

Same for designing a decade/BCD counter. Designing a counter doesn't involve using reset (unless reset is to reset the counter at any count). All you did was sling gates.

This is how I'd design a decade counter:

The logic simulator I use assigns a LOW to unconnected pins, so I left the set and clear inputs of the D FF unconnected to make the schematic easier to read.

EDIT: JK was even simpler:

 

I didn't do much of anything and I still don't think that's what your teacher intended for either project.

There's little learning if you use a 4 bit adder IC instead of designing and cascading a 1 bit adder.

Same for designing a decade/BCD counter. Designing a counter doesn't involve using reset (unless reset is to reset the counter at any count). All you did was sling gates.

This is how I'd design a decade counter:
View attachment 213112
The logic simulator I use assigns a LOW to unconnected pins, so I left the set and clear inputs of the D FF unconnected to make the schematic easier to read.

EDIT: JK was even simpler:
View attachment 213114

Well, i talked to her and she said I've done it right and exactly as she wanted.

And about your circuits, I'm not much of a designer as you know but I'll try to find the differences between your design and mine as soon as i finished this term
Wish you all the best man, keep up your great work.

 

And about your circuits, I'm not much of a designer as you know but I'll try to find the differences between your design and mine as soon as i finished this term

I'm always interested in helping those who really want to learn and would be glad to help you with any questions.

I understand this isn't in your major. I certainly hope the technical classes I took in college outside of my major weren't as dumbed down as what you're taking as an EE elective. When I was at SJSU, non-EE majors were taking some of the same classes I was taking. They had the opportunity to learn as much as I did, but most of them just wanted to get a passing grade.

Does Proteus have an option for printing to PDF? That grid and background color aren't very pleasing to the eye.

When I studied electronics, we were required to take a drafting class for a term. We were taught how to draw schematics that were readable. The main emphasis was on having the flow be predominantly from left to right and top to bottom while minimizing unnecessary wire jogs and scenic routing. Your schematic is tedious to follow.

If you're going to design a 2 digit counter, I prefer to do something like this so the digits are right reading:

Note how I have labeled the terms for each AND gate. That makes it easier for me to troubleshoot logic/wiring mistakes and for someone else to follow the logic.

Here's an example where I intentionally violated the left to right rule to make the display more readable:

This is a 24 hour up/down clock. Down doesn't make much sense unless it was to be used as a timer, but that was what the problem required.

 

Does Proteus have an option for printing to PDF? That grid and background color aren't very pleasing to the eye.

Wow man, your a total pro
IDK if Proteus has such an option, but i can upload both .pdsprj files in my Google drive and share their links here if you want.

 

Wow man, your a total pro

Thanks, but I can't take all of the credit. I read a lot of logic diagrams from TI, RCA, Motorola, and others and developed my style from what I liked from what I read.

Schools don't seem to have much interest in teaching how to draw readable schematics. I've seen some ghastly schematics drawn by teachers.

IDK if Proteus has such an option, but i can upload both .pdsprj files in my Google drive and share their links here if you want.

Proteus isn't a free simulator, so that won't be useful to anyone who doesn't have Proteus. Me being one of them. I do this for a hobby and only use free software.