Post your work for the counter design. If you're not sure where to start or what to do, you can bounce ideas off us.

When is this assignment due?

Ok, thanks for your help, really
I'm awaiting her email to know which way i should do it.
As soon as i got news, I'll design a new circuit and will share it right here.
Also the deadline is less than a week from today...

 

Also the deadline is less than a week from today...

That should be plenty of time. I design circuits in this section for fun and it usually takes more time to get requirements from students than to actually implement the counter.

You said you needed to use D flip flops, but your simulations show JK. You're using the reset inputs on the flip flops, but you don't need to do that when you design a counter (unless the problem requires a reset function).

 

So here is the schematic of the first project and it should get A and B (both 4 bit binary numbers from 0000 to 1001) and do A+B and A-B and if the result magnitude is negative, show (-) sign before the number.

selected parts (red ones) are to produce (-) sign for subtracting exceptions like 0-9 or 0-0
But some of them still exist, like 8-0 or 9-0 produce the negative sign too.

I also wanted to use a comparator IC, but again my professor told me not to do...

I copied your schematic and excluded the simulation on 74185 and adding in my version with a 2732 eprom ( the smallest prom on my proteus) and it seems to work well as attached.

No idea what the rest of the logic gates are doing so I didnt do anything on them.
The hex file for the eprom data is also attached, if you want to try it out.

Allen

 

I also wanted to use a comparator IC, but again my professor told me not to do...

But she's okay with you using an adder IC?? Teachers usually want students to design a single bit adder and cascade it to 4 bits.

 

i connected the VCC and GND of them to power source to test if they are working, the outputs were continuesly changing from 1 to 0 and back

Were any of the address lines floating? Was enable LOW? Did you know that the outputs are open collector?

When you're discussing circuits, even simple ones, it's best to post a schematic so we don't have to play 20 questions.

 

That should be plenty of time. I design circuits in this section for fun and it usually takes more time to get requirements from students than to actually implement the counter.

You said you needed to use D flip flops, but your simulations show JK. You're using the reset inputs on the flip flops, but you don't need to do that when you design a counter (unless the problem requires a reset function).

Well i had a private class with my professor lately and she helped me a bit so i finally made it and will share the resulta ASAP.
Also, any type of flip flops is ok to use and she said it has to reset itself from 99 back to 0.

 

I copied your schematic and excluded the simulation on 74185 and adding in my version with a 2732 eprom ( the smallest prom on my proteus) and it seems to work well as attached.

No idea what the rest of the logic gates are doing so I didnt do anything on them.
The hex file for the eprom data is also attached, if you want to try it out.

Allen

View attachment 212349

WOW man, thanks a lot
That's a lot for me to understand...
But I'll do my best
Also i have to mention that I'm not allowed to use eprom and the problem is solved as i said.
The problem was so easier than i thought...
I'm not suppose to make 7 bit binary and convert it to BCD, instead i made two row of 4 JKFFs which produce 8 bit (2 digit) BCD from the begining.
I'll post the schematic if it works in reality
Thanks again for your reply tho

 

But she's okay with you using an adder IC?? Teachers usually want students to design a single bit adder and cascade it to 4 bits.

I have no idea, she's a tough one as someone in this thread mentioned before
Yet, i donno what's wrong with her, i just do what she wants to pass the da#n course...

 

You were expected to design an FSM (finite state machine). Somehow you must have missed that lecture.

 

Were any of the address lines floating? Was enable LOW? Did you know that the outputs are open collector?

When you're discussing circuits, even simple ones, it's best to post a schematic so we don't have to play 20 questions.

I'm sorry again about the schematic...

It was reset HIGH, and i made them all HIGH from the begining by mistake

 

You were expected to design an FSM (finite state machine). Somehow you must have missed that lecture.

I never heard of a FSM ever TBH

 

This is an engineering course. She is teaching you engineering methodology.
You get the facts straight. You cover the essentials needed to solve the problem. You settle on a viable solution. If the solution looks complicated you look for alternatives.

Jumping into a coal mine with a shovel and pickaxe is not engineering.

A FSM has finite states.
A 0-to-99 counter has 100 finite states. How many flip-flops would it require to have 100 unique states?
State-0 advances to State-1, and so on.
All computer architecture is based on FSM. This knowledge is essential to biomedical engineering, though you do not appreciate it.

 

This is an engineering course. She is teaching you engineering methodology.
You get the facts straight. You cover the essentials needed to solve the problem. You settle on a viable solution. If the solution looks complicated you look for alternatives.

Jumping into a coal mine with a shovel and pickaxe is not engineering.

A FSM has finite states.
A 0-to-99 counter has 100 finite states. How many flip-flops would it require to have 100 unique states?
State-0 advances to State-1, and so on.
All computer architecture is based on FSM. This knowledge is essential to biomedical engineering, though you do not appreciate it.

Well as you said, i realized i already knew it, but didn't know the word FSM
And of course i appreciate it!
But it's just taking me too long
I'm knida tired and need some holidays to spare with friends and family after three months, that's the reason im acting kinda rushed i guess, and I'm not proud of it

 

Just remember, one’s attitude can tell us a lot about one’s personality.
Hope you get your well earned break.

 

I'm knida tired and need some holidays to spare with friends and family after three months,

Don't jeopardize your future by being short sighted. School is more important than spending time with friends and family.

I worked my way through college and had almost a full time job. I had little time for friends and family. Working after I graduated seemed like a vacation for the first year. I worked in the SF Bay Area and could go to work at around 0600 and be off at 1430. Had time to go to the beach after work if I wanted to; and sometimes did. After that, I transferred to an R&D position and didn't have the start time flexibility or the weekly "beer busts". By then, I had started taking evening classes, so it was back to the old grind of only having time for work and school.

 

School is more important than spending time with friends and family.

Let's rephrase that:
Spending time with friends and family is more important than school or work - It is finding the right balance and knowing when one takes priority over the other.

 

Let's rephrase that:

Yeah, nothing's ever black and white. I still prioritized school over socializing.

 

Yeah, nothing's ever black and white. I still prioritized school over socializing.

That’s ok. It just shows your personality type. You are an I-type and not an E-type. I-types get their energy from within. E-types get their energy from the people they mix with.

 

That’s ok. It just shows your personality type. You are an I-type and not an E-type. I-types get their energy from within. E-types get their energy from the people they mix with.

Speaking of personality types, I'm an ENFJ

 

Dear @dl324
Here is the last schematic i designed for the first project that we discussed before in this thread, but still 7-segments receive inputs and show nothing!!!
Can you pls take a look at it?!
Link: https://gofile.io/d/XppVSD