Nothing will happen, the D-type flip flop is edge-triggered - in the absence of a clock edge the output will remain the same.1. if the clock is low, how it will affect the output?
On successive clock-edges the input D and output Q will switch from one state to another, i.e. 0-1-0-1-0-1....2. if D is connected to NOT Q, what does it mean?
The end result of this connection scheme as dave has so ably stated is that the output of the latch divides the incoming clock signal by two.2. if D is connected to NOT Q, what does it mean?
huh? what is the meaning of divides the incoming clock signal by 2??The end result of this connection scheme as dave has so ably stated is that the output of the latch divides the incoming clock signal by two.
hgmjr
Oooppppssss!huh? what is the meaning of divides the incoming clock signal by 2??
does it mean that NOT Q will send signal to D then Q will follow D?On successive clock-edges the input D and output Q will switch from one state to another, i.e. 0-1-0-1-0-1....
Dave
Yes, but Q will only follow the change on D at the clock edge - this is a fundamental feature of flip-flops that differentiate them from other such devices such as latches.does it mean that NOT Q will send signal to D then Q will follow D?
by Jake Hertz
by Duane Benson
by Aaron Carman
by Jake Hertz