ESR variation of photoflash capacitors placed in series RLC discharge circuit

Thread Starter


Joined Mar 3, 2020

I plan to design a series RLC discharge circuit as shown:

Taking into account component parasitics, the actual circuit resembles the following:
equivalent circuit.jpg

  1. 'R' = capacitor ESR + load resistance + inductor ESR,​
  2. 'L' = capacitor ESL + load inductance ≈ load inductance​

According to online sources, capacitor ESR is calculated using the equation below:
esr equation.jpg
I plan to use photoflash capacitors as they are designed to discharge high current pulses and so have lower ESR compared to regular electrolytic capacitors. In a typical datasheet (e.g., the dissipation factor, tan(δ) is given to be 0.2. By substituting the test frequency (120 Hz) and the capacitance (0.003 F), the ESR is calculated to be 88.4 mΩ. This value is rather high for my application, which aims to drive a load smaller than 10 mΩ. This can result in excessive power dissipation across the capacitor and generate significant thermal stress that shortens its service life.

If the equivalent values of R, L and C are such that the circuit goes into an underdamped discharge, then the effective oscillation frequency of the current pulse will be given by the equation:
oscillation frequency.jpg
Does this mean that:
(1) the underdamped frequency will now be equivalent to the 'test frequency' applied across the capacitor, and
(2) the ESR of the capacitor will change according to circuit current's underdamped frequency?
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Joined Jan 29, 2010
hi f20,
Interesting project, is this related to the LTSpice sim work.?
May I ask what will be the purpose this project, when finished.?

Thread Starter


Joined Mar 3, 2020
hi eric, this query is related to the ltspice simulation in a previous thread and the project aims to design an efficient capacitor based pulse power supply that matches a relatively high impedance capacitive supply to a low impedance RL load - feel free to message me privately!
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