Hello,

There is an easier way if you do not care about waiting a little longer for a reading.
That is to provide a 1/2 Hz gate pulse. That's one second high and one second low.
During say the high state, the counter is counting while the latches hold the previous count.. During the low state, the counter is latched and displaying the previous count.
Once you get that working, it's just a matter of starting the reset and pulse timing a little sooner. It will be the same except the low state will be shorter.
You do have to be careful if you use series capacitors for one-shots. If you do anything like that you should really use Schmitt trigger input gates.

 

Hi
Proposed Main Gate Circuit
M

 

Here is a timing diagram of an unsynchronized input clock signal.

Let us assume that the counter changes state on the rising transition of the CLOCK signal.
Let us make the RESET interval exactly two clock periods (N = 2). It doesn't matter when the RESET signal appears (i.e. not synchronized), the counter will always see 2 rising edges, hence the counter registers correctly N = 2.

However, if the RESET signal appears exactly at the same time as the rising edge of the CLOCK, the counter could count 1 or 2 rising edges and there is nothing one can do to change this, i.e. there is nothing to fix.

 

Hello,

There is an easier way if you do not care about waiting a little longer for a reading.
That is to provide a 1/2 Hz gate pulse. That's one second high and one second low.
During say the high state, the counter is counting while the latches hold the previous count.. During the low state, the counter is latched and displaying the previous count.
Once you get that working, it's just a matter of starting the reset and pulse timing a little sooner. It will be the same except the low state will be shorter.
You do have to be careful if you use series capacitors for one-shots. If you do anything like that you should really use Schmitt trigger input gates.

That's basically with I did with my old (~50 years) frequency counter.

Woops, took the picture up-sides down.

https://forum.allaboutcircuits.com/threads/lets-talk-about-frequency-counters.136965/post-1145966

She's still counting.

 

I took a similar approach on my frequency counter. I did not want to add latches in my design.
Hence I counted for a fraction of a second (I believe for 100ms) and then displayed the result for 900ms (or something like that).

 

my first frequency counter was also done with TTL. don't have the unit any more but the gate time was used to count, the latch and reset pulses were produced while the gate was low. worked fine.

 

I took a similar approach on my frequency counter. I did not want to add latches in my design.
Hence I counted for a fraction of a second (I believe for 100ms) and then displayed the result for 900ms (or something like that).

I am totally lost. I have no idea how to proceed. I also have no room to add latches if they are required.

 

I am totally lost. I have no idea how to proceed. I also have no room to add latches if they are required.

Your design is fine as a learning project. Use what you think is right for your design.

 

I am totally lost. I have no idea how to proceed. I also have no room to add latches if they are required.

Don't despair. We're here to help.

The traditional design of a frequency counter would consist of a counter, latch, and decoder-driver ICs.
There are chips that have all three components in one package, e.g. CD40110B.
Fortunately, CD4511 has the latch and decoder-driver in the one package.

With a 1Hz time-base, you will be able to display frequency in Hz.
What you need is a short /LATCH ENABLE signal and a RESET signal at 1-second intervals.

If you look at the datasheet of CD4511 you will see /LE on pin-5.



Hence you need /LE which is a short downward pulse (5V - 0V - 5V), followed by a upward going RESET pulse (0V - 5V - 0V).

Look at post #9 to see how to generate these pulses using AND, NAND and NOT gates. Use your oscilloscope to confirm that your design ideas are working. Test the pulse circuits by applying signals at say, 1000Hz or even faster (not the 1Hz time base).

Remember, you don't need 1ns pulse widths. Pulse widths of 100ns to 500ns would be fine.

 

Don't despair. We're here to help.

The traditional design of a frequency counter would consist of a counter, latch, and decoder-driver ICs.
There are chips that have all three components in one package, e.g. CD40110B.
Fortunately, CD4511 has the latch and decoder-driver in the one package.

With a 1Hz time-base, you will be able to display frequency in Hz.
What you need is a short /LATCH ENABLE signal and a RESET signal at 1-second intervals.

If you look at the datasheet of CD4511 you will see /LE on pin-5.

View attachment 316190

Hence you need /LE which is a short downward pulse (5V - 0V - 5V), followed by a upward going RESET pulse (0V - 5V - 0V).

Look at post #9 to see how to generate these pulses using AND, NAND and NOT gates. Use your oscilloscope to confirm that your design ideas are working. Test the pulse circuits by applying signals at say, 1000Hz or even faster (not the 1Hz time base).

Remember, you don't need 1ns pulse widths. Pulse widths of 100ns to 500ns would be fine.

Thanks MrChips. Do I keep the circuit that I connected to pin #9 (reset pin) of each CD4510 that ensures the
counter will begin counting at zero or will there be a conflict when I connect the reset signal from the main gate circuit?
I will continue to work on this!
M

 

some notes:

the signals that have a line above them are inverted. in this case LT, BL and LE are such signals. this means they are active when low. in your schematics they are inactive (held high). as MrChips suggested, separate LE from the +5V and use it to latch the data.
when latched, counter values will be displayed and frozen until next latch pulse. this means you want to latch before reset (otherwise displays will be "fuzzy" - show zero and counting up).

your schematics already has latch and reset signals and they are of correct polarity but .... they are derived of the gate time. (Q2 of CD4013) and while that can work, it is not ideal because end of displayed value will be glitchy. you do not want the length of the latch and reset signals to interfere with counting. as stated in post 26, you want to generate the latch and reset pulses after counting is done - while the gate signal is low.

so my suggestion is to connect the capacitor to pin12 instead of pin 13 (that is Q2 inverted - a complementary of gate time).

 

Thanks MrChips. Do I keep the circuit that I connected to pin #9 (reset pin) of each CD4510 that ensures the
counter will begin counting at zero or will there be a conflict when I connect the reset signal from the main gate circuit?
I will continue to work on this!
M

I believe what you are referring to is the POWER-ON RESET circuit. You will no longer need this because the counters will be reset once every second anyway.

@panic mode has shown one way of deriving /LE and RESET from the 1Hz time-base.
The input CLOCK signal is also gated with the time-base. You can try this but I think it is not necessary. I would feed the CLOCK signal straight to the counters.

 

If you did not have latches to latch the count, you could stop the count for a second or two to read it, but you'd see a blur of digits while it was counting which may or may not be objectionable.

You can also use shorter or longer gate pulse timings. Using 0.1 second you get a frequency count that is f/10, and using 10 seconds you get a count that is f*10. The f*10 is useful when you have lower frequencies and you want to get better resolution. With a 10 Hz signal and 1 second gate you get a count of 000010 but with a 10 second gate you get 000100 which divided by 10 mentally (or providing a decimal point) you get 10.0 Hz. If it was really 10.3 Hz then you would see a count of 000103 rather than just 000010.

Here is a picture of the inside of my home built 8 digit frequency counter. The display is made of 7 segment LED displays.
The TTL chips are a counter, a latch, and a multiplexing gate which only requires one 7 segment decoder and some glue logic.

 

I built the following circuit to provide the latch and reset pulses. I scoped the test frequency and the
latch and reset pulses such as they are.

 

CHAN 2 is meaningless.
Don't set CHAN 2 input to 50mV. Set all channels to 2V or 5V.
When I get a chance I will breadboard something for you.

BTW, CHAN 2 colour is magenta. CHAN 3 colour is cyan.

 

CHAN 2 is meaningless.
Don't set CHAN 2 input to 50mV. Set all channels to 2V or 5V.
When I get a chance I will breadboard something for you.

BTW, CHAN 2 colour is magenta. CHAN 3 colour is cyan.

Thanks MrChips!

 

Treat this as a learning exercise. The objective is to learn how to design your own digital circuits and at the same time become familiar with using the oscilloscope.

Here is one circuit designed in four steps, 1, 2, 3, and 4.



STEP 1 - Connect a fast CLOCK signal into both inputs of a CD4011 NAND gate. Observe and measure on the oscilloscope the time delay between the input and output signals on both the rising and falling edge of the input signal. In other words, trigger the oscilloscope on the input signal (CHAN 1) and examine the output signal on CHAN 2.

STEP 2 - Add a resistor to one of the two inputs. Repeat as per STEP 1.

STEP 3 - Add a capacitor as per the circuit. In addition to measuring the time delay, observe the signal at the capacitor.

STEP 4 - Here we AND the original CLOCK signal with the DELAYED CLOCK signal (and output the inverted AND). Measure the pulse width of the inverted pulse. Draw on paper the timing diagram of the signals observed at pins 5, 6, and 4, and include the time scale.

 

Treat this as a learning exercise. The objective is to learn how to design your own digital circuits and at the same time become familiar with using the oscilloscope.

Here is one circuit designed in four steps, 1, 2, 3, and 4.

View attachment 316264

STEP 1 - Connect a fast CLOCK signal into both inputs of a CD4011 NAND gate. Observe and measure on the oscilloscope the time delay between the input and output signals on both the rising and falling edge of the input signal. In other words, trigger the oscilloscope on the input signal (CHAN 1) and examine the output signal on CHAN 2.

STEP 2 - Add a resistor to one of the two inputs. Repeat as per STEP 1.

STEP 3 - Add a capacitor as per the circuit. In addition to measuring the time delay, observe the signal at the capacitor.

STEP 4 - Here we AND the original CLOCK signal with the DELAYED CLOCK signal (and output the inverted AND). Measure the pulse width of the inverted pulse. Draw on paper the timing diagram of the signals observed at pins 5, 6, and 4, and include the time scale.

Thanks. Looking forward to this!
M

 

Treat this as a learning exercise. The objective is to learn how to design your own digital circuits and at the same time become familiar with using the oscilloscope.

Hi:

I tried step #1. Input 4 vpp, 1Khz 50% DC
Scope set to trigger on channel 1 rising edge
Lots of jitter and freq per scope = 13.9 Khz

M

 

Not jitter.
Ignore the scope frequency readout of f = 13.8886kHz

Look at the waveform on the oscilloscope screen. TIME/DIV is set to 1ms. Screen shows one cycle in 1ms which is 1kHz.
The mean voltage is 4.97V with an amplitude of 0.3V.

Looks like you are missing a GND connection on your IC.