Hi:

I have built a 6-digit counter circuit with a 1Hz timebase. See attached image.
The final step in my frequency counter circuit is that of building an Input circuit
and a Main Gate circuit and then connecting them to the 6-digit counter. I have
attached a schematic of the complete circuit as I envision it. Please let me know
what you think of it and I am open to any suggestions.

Thanks,

M

 

When it comes to designing sequential circuits such as this one, it is helpful for yourself and others to draw a timing diagram.

In other words, you need to show time-base, start counting, stop counting, gate, latch, and reset signals.

Here is an example of a timing diagram.

 

I have
attached a schematic of the complete circuit as I envision it.

Your schematic is incomplete because it doesn't indicate pin function. I don't have it memorized for CD4510, so I need to refer to the datasheet before I can comment...

It's customary to put pin function inside of the symbol and pin numbers on the outside.

 

When it comes to designing sequential circuits such as this one, it is helpful for yourself and others to draw a timing diagram.

In other words, you need to show time-base, start counting, stop counting, gate, latch, and reset signals.

Here is an example of a timing diagram.

View attachment 315993

Hi Mr Chips

Here is my main gate timing diagram.

M

 

Here is a circuit that I simulated and ran a plot. I am not sure if the Reset pulse occurs after the Load (Latch) pulse.

 

The timing is not necessarily how the circuit behaves after it has been designed, in other words, don't use the simulator output.

The timing diagram comes before the design. It represents how YOU want the circuit to function. The design follows from the timing diagram.

RESET should come after the LATCH signal.

The sequence is: COUNT - LATCH - RESET

 

Hi Mr Chips

Here is my main gate timing diagram.

M

How stable is the count with that gate circuit? You might want to look at a simple gate synchronizer to eliminate bobble.


https://archive.org/details/TTLCookBook

https://web.stanford.edu/class/ee183/handouts_spr2003/synchronization_pres.pdf

 

How stable is the count with that gate circuit? You might want to look at a simple gate synchronizer to eliminate bobble.
View attachment 316004

https://archive.org/details/TTLCookBook

https://web.stanford.edu/class/ee183/handouts_spr2003/synchronization_pres.pdf

Thanks nsaspook. Since I am using a CD4013, I am not sure what resistor values to use.
I have attached a simulation but it doesn't seem to be working right with the values
that TTL Cookbook uses with the 7474 chip. So I just changed the values but still no
luck.

M

 

Thanks nsaspook. Since I am using a CD4013, I am not sure what resistor values to use.
I have attached a simulation but it doesn't seem to be working right with the values
that TTL Cookbook uses with the 7474 chip. So I just changed the values but still no
luck.

M

Those RC values are for generating edge trigger pulses, don't know off hand what the equivalent values would be for CMOS. If it doesn't work, not big deal, It's just something I had on my old frequency counter.
https://forum.allaboutcircuits.com/threads/lets-talk-about-frequency-counters.136965/post-1145966


You can try delay edge trigger generation for the same effect if you want to play around a bit.
https://www.allaboutcircuits.com/textbook/digital/chpt-10/edge-triggered-latches-flip-flops/

 

What resistors are you referring to? In circuit schematics, you need to specify component identifiers such as R1, C2, U3, etc. so that we can refer to specific components.

7400 series and CD4000 series ICs are very different. You cannot use the same value resistors in a 7400 series circuit and transfer those to CD4000 series circuits.

 

Hi
What resistors are you referring to? In circuit schematics, you need to specify component identifiers such as R1, C2, U3, etc. so that we can refer to specific components.

7400 series and CD4000 series ICs are very different. You cannot use the same value resistors in a 7400 series circuit and transfer those to CD4000 series circuits.
I am referring to the four resistors (R1 through R4) in the attached circuit which was suggested as a replacement for the main gate circuit
that I posted earlier. I did the sim to see if the circuit was even close to being suitable but it doesn't look right to me.

M

 

Your schematic would be easier to read if you drew it more like this:

 

The timing is not necessarily how the circuit behaves after it has been designed, in other words, don't use the simulator output.

The timing diagram comes before the design. It represents how YOU want the circuit to function. The design follows from the timing diagram.

RESET should come after the LATCH signal.

The sequence is: COUNT - LATCH - RESET

Hi:

The brief high to low (latch or load) pulse needs to happen nano seconds after
the rising edge of the clock pulse and the brief low to high reset pulse needs
to happen right after that. These two pulses need to happen such that the counter
does not miss counting the first frequency input square wave. I have no idea
how to accomplish that. I have played around with various circuits in Spice. I
thought that I could use a CD4093 NAND With Schmitt Trigger but the resultng
pulses happen far too late. I think that an RC network is required to get the
timing correct.

M

 

post 9 shows how use gate propagation time to create delay

 

You are splitting hairs here.

Look up the maximum CLOCK frequency of the counter IC.
If you are using CD4510B, then CLOCK max is 2MHz. One period is 500ns.

All counting systems will have an error of 0-1 count because there is always a finite probability that the gate is just too early or too late.

Thus, your counting interval is the time duration between two consecutive RESET pulses. The width of the LATCH and RESET pulses can be as long as 100ns before you notice any difference to the accuracy of the system.

 

You are slitting hairs here.

Look up the maximum CLOCK frequency of the counter IC.
If you are using CD4510B, then CLOCK max is 2MHz. One period is 500ns.

All counting systems will have an error of 0-1 count because there is always a finite probability that the gate is just too early or too late.

Thus, your counting interval is the time duration between two consecutive RESET pulses. The width of the LATCH and RESET pulses can be as long as 100ns before you notice any difference to the accuracy of the system.

Is this circuit correct?

 

You are slitting hairs here.

Look up the maximum CLOCK frequency of the counter IC.
If you are using CD4510B, then CLOCK max is 2MHz. One period is 500ns.

All counting systems will have an error of 0-1 count because there is always a finite probability that the gate is just too early or too late.

Thus, your counting interval is the time duration between two consecutive RESET pulses. The width of the LATCH and RESET pulses can be as long as 100ns before you notice any difference to the accuracy of the system.

That last digit bobble can be eliminated from the counting system using a synchronizer. Digital bit synchronizer circuits are often used with data stream devices to lock the incoming data embedded clock (with random transmission jitter) to a stable decoding clock.

https://ia802602.us.archive.org/0/items/donlancaster_frequency_count_34_69/frequency_count_34_69.pdf
HIGH-ACCURACY COUNTING TO 2 MHz BY DON LANCASTER

A special electronic synchronizer eliminates variations in the display of the last digit (known as bobble).

 

You do not need to synchronize to the incoming signal.

If the gate is short of N cycles, you will get N-1 counts.
If the gate is over N cycles but shorter than N+1 cycles, you will get N counts.

The last digit bobble occurs when the gate period is exactly N cycles. The 0/1 error is unavoidable, synchronized or not synchronized.

 

You do not need to synchronize to the incoming signal.

If the gate is short of N cycles, you will get N-1 counts.
If the gate is over N cycles but shorter than N+1 cycles, you will get N counts.

The last digit bobble occurs when the gate period is exactly N cycles. The 0/1 error is unavoidable, synchronized or not synchronized.

Let's just say I think I will stick with what Lancaster said and built In 1969 instead. His circuit worked for me long ago and his explanation of how and why is logical.

 

I admire and respect Don Lancaster and I have a number of his books.
I will read over and study what he has to say.

I built my own RF frequency counter that measured the local oscillator frequency of my SW radio and it adjusts for the IF thus showing correct radio frequency received.