I am very new to VHDL and I am trying to code a MUX, I am close but need a little help
Rich (BB code):
Library ieee;
Use ieee.std_logic_1164.all;
Entity Mux is
Port(
D : in std_logic_vector(4 downto 0);
Y : out std_logic_vector(1 downto 0));
End Mux;
Architecture Joe_Structure of Mux is
Begin
with D select
Y<= "I0" when "00",
"I1" when "01",
"I2" when "10",
"I3" when "11";
End Joe_Structure;