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I am developing a finite state machine (FSM) in VHDL to control a circuit, but I am facing an issue where the initial START state never transitions, even when the GO signal is set to '1'.
The states in my FSM are: START, INIT, TEST, YMINX, XMINY, and RES. When the GO signal is activated, I expect the FSM to transition from START to INIT. However, the circuit gets stuck in the START state and does not move forward, no matter the state of GO.
I expect the FSM to transition from START to INIT when GO = '1', but this isn't happening. What am I missing? Could it be an issue with how GO is being handled, or is there something else in my code causing this problem? Any help or insight would be appreciated!
The states in my FSM are: START, INIT, TEST, YMINX, XMINY, and RES. When the GO signal is activated, I expect the FSM to transition from START to INIT. However, the circuit gets stuck in the START state and does not move forward, no matter the state of GO.
VHDL code:
-- Entity definition
entity pc is
port (
CLK: in std_logic;
GO: in std_logic;
RST: in std_logic;
XEQY_IN : in std_logic;
XETY_IN: in std_logic;
SEL_OUT: out std_logic;
SEL_XY_OUT: out std_logic;
LOAD_X_OUT: out std_logic;
LOAD_Y_OUT: out std_logic;
DONE : out std_logic
);
end entity;
-- Architecture definition
architecture Behaviour of pc is
type ESTADOS is (START, INIT, TEST, YMINX, XMINY, RES);
signal etat_actual, etat_prochaine : ESTADOS;
begin
clock_process :process(CLK, RST)
begin
if RST = '1' then
etat_actual <= START;
elsif rising_edge(CLK) then
etat_actual <= etat_prochaine;
end if;
end process clock_process;
transition_etats: process(etat_actual, GO, XETY_IN, XEQY_IN)
begin
case etat_actual is
when START =>
if GO = '1' then
etat_prochaine <= INIT;
else
etat_prochaine <= START;
end if;
when INIT =>
etat_prochaine <= TEST;
when TEST =>
if (XETY_IN and XEQY_IN) then
etat_prochaine <= TEST;
elsif (not XETY_IN and not XEQY_IN) then
etat_prochaine <= YMINX;
elsif (XETY_IN and not XEQY_IN) then
etat_prochaine <= XMINX;
elsif (not XETY_IN and XEQY_IN) then
etat_prochaine <= RES;
else
etat_prochaine <= TEST;
end if;
when YMINX =>
etat_prochaine <= TEST;
when XMINX =>
etat_prochaine <= TEST;
when RES =>
etat_prochaine <= RES;
when others =>
etat_prochaine <= RES;
end case;
end process transition_etats;
sorties : process(etat_actual)
begin
case etat_actual is
when START =>
SEL_OUT <= '0';
LOAD_X_OUT <= '0';
LOAD_Y_OUT <= '0';
SEL_XY_OUT <= '0';
DONE <= '0';
when INIT =>
SEL_OUT <= '1';
LOAD_X_OUT <= '1';
LOAD_Y_OUT <= '1';
SEL_XY_OUT <= '0';
DONE <= '0';
when TEST =>
SEL_OUT <= '0';
LOAD_X_OUT <= '0';
LOAD_Y_OUT <= '0';
SEL_XY_OUT <= '0';
DONE <= '0';
when XMINY =>
SEL_OUT <= '0';
LOAD_X_OUT <= '1';
LOAD_Y_OUT <= '0';
SEL_XY_OUT <= '1';
DONE <= '0';
when YMINX =>
SEL_OUT <= '0';
LOAD_X_OUT <= '0';
LOAD_Y_OUT <= '1';
SEL_XY_OUT <= '0';
DONE <= '0';
when RES =>
SEL_OUT <= '0';
LOAD_X_OUT <= '0';
LOAD_Y_OUT <= '0';
SEL_XY_OUT <= '0';
DONE <= '1';
end case;
end process sorties;
end architecture;
