VHDL 4 input 1 output MUX

Thread Starter

gammaman

Joined Feb 14, 2009
29
I am very new to VHDL and I am trying to code a MUX, I am close but need a little help

Rich (BB code):
Library ieee;
Use ieee.std_logic_1164.all;
Entity Mux is
   Port(
       D : in std_logic_vector(4 downto 0);
       Y : out std_logic_vector(1 downto 0));
End Mux;
Architecture Joe_Structure of Mux is
Begin
   with D select
   Y<= "I0" when "00",
       "I1" when "01",
       "I2" when "10",
       "I3" when "11";
End Joe_Structure;
 

silvrstring

Joined Mar 27, 2008
159
'D' is not your select. 'D' is only the signal inputs. You need to add another 'in' variable for the select. In your Entity, put 'S' where 'Y' is, and make it an 'in' instead of 'out.' You will still need 'Y' for your 'out,' though. But Y is not a vector. Maybe "std_logic".

In your Architecture, 'S' is going to be your select, not 'D.'

Also, I think your y<= "I0" when "00" etc., statements should be y<= D(0) when "00" and so on.
Try finishing with "'0' when others;"

Not sure what version of Quartus you're using, but you might also want to download the latest trial. It has less problems.
 
Last edited:

silvrstring

Joined Mar 27, 2008
159
By the way, the example I'm looking at is from an older text. Some things are different with Quartus now. If there's still a problem, it's probably going to be the "I0" thing versus using D(0)...

If you try both and there's still a problem, you probably want to try different data types in your Entity. Let me know how it goes.
 

Thread Starter

gammaman

Joined Feb 14, 2009
29
Yeah when I compiled in Quartus II the only errors I got delt with the I0 to I3, it said I could not use the letter I, but I do not know how else to represent it.
 

Thread Starter

gammaman

Joined Feb 14, 2009
29
No, I get the same error as before, it says that the letter "D" is not allowed.

Error (10315): VHDL syntax error at Mux.vhd(14,15,16,17): object with std_logic type, cannot contain character 'D'
 

veritas

Joined Feb 7, 2008
167
In your example, you have "I0" like that in quotes. Anything in quotes is taken as a literal string, usually of binary. If you have a variable D of type std_logic_vector, then you can access the individual bits of D with D(index).
 

silvrstring

Joined Mar 27, 2008
159
gammaman,

This example comes directly out of the book. I compiled it, and it came back okay.

Try it like this. If it still doesn't compile, you might want to check for updates or download the latest version of Quartus from Altera.com


Library ieee;
Use ieee.std_logic_1164.all;

Library ieee;
Use ieee.std_logic_1164.all;

Entity Mux is
Port(
D : in std_logic_vector(4 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
End Mux;

Architecture Joe_Structure of Mux is
Begin
with S select
Y<= D(0) when "00",
D(1) when "01",
D(2) when "10",
D(3) when "11";
End Joe_Structure;
 

tuborggg

Joined Jan 3, 2009
37
BTW, there's a bit spare, D(4)...I'm guessing you wanted to define it 3 downto 0 for 4 bit usage
 
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