I'm not a PHD nor EE, but I did say it was a 2 cent model. I suspect we'd get the same answers.

ltspice is free, I run it on Linux with wine. Here's a screen shot and the ltspice file. The 6n capacitor and inductor really ring...

 

That's awesome michael! You beat me to the simulation by at least a day.

Now, I see you're using 12V as Vdd but my model for the 6nF shunt cap only works if we're at much much fast rise times.

My testing will start at 24V and gradually move to 30V, 35V, 40V ... not sure I'll get to 50V for reasons we've been discussing and in particular because breakdown Vds is 100V for each FET. In any case, when I proposed the 6nF cap it was for much faster rise time. Since I haven't setup TINA-IT yet, can you try for 30V or 35V?

Thanks!!!

 

And I'm sure there will be some ringing no matter what. I need to play around with a resistor in series with the cap. 1k was where I was going to start.

 

In any case, you're showing voltage when all i care about is current flow through the coil and of course not damaging the FETs. I don't mind large voltage swings (although not as in your results shown), but after cutoff current isn't flowing at X except where |EMF| > 12V. So it's current profile across the coil that i'm interested in at higher voltage.

 

More to the point, for all points after cutoff where |EMF| < 12V those swings are due to Vd of each FET swinging up and down with each other. But almost no current at all flowing since Rds is extremely high and diode protection isn't conducting.

 

> #22 You beat me to the simulation by at least a day.

My first simulation (not shown) was yesterday. I was unsure
the effect/clamping voltage of the mosfet diodes.

I don't see any danger to the fets other than having both on at once
(or possibly very slow switching). The diode in the other will clamp
the EMF close to Vdd which they can handle. So at Vdd of 60 volts the
peak on the off fet is 60+one diode drop.

This assumes reasonable wiring which doesn't introduce extra inductors
everywhere. For example a long wire from a fet drain to the junction
with the other fed drain/coil would be an inductor without a clamp diode.
A fast enough turn off of the fet wouldn't be clamped (locally). A wire
has about 1 nH/mm of inductance...

> #23 And I'm sure there will be some ringing no matter what. I need to play
> around with a resistor in series with the cap. 1k was where I was going
> to start.

I used .1uF and 1K (yesterday) which seemed fine.

> #24 you're showing voltage when all i care about is current
> flow through the coil

Here's a new screen capture, Vdd 60 volts, pulse 500 uS. The current
only reaches 350 mA and that for only a moment.

 

I believe I have a diode solution to the excessive Vd swings. Hope to have that posted soon.

 

> #26 I don't see any danger to the fets other than having both on at once
> (or possibly very slow switching). The diode in the other will clamp
> the EMF close to Vdd which they can handle. So at Vdd of 60 volts the
> peak on the off fet is 60+one diode drop.

Ooops... I'm wrong since the fet source is at -Vdd and the drain
at +Vdd+Vdiode, about 2*Vdd, so over 50 volts is too much and
I'd want some margin.

Also beware that when the fet drain voltage changes that feeds
through the drain to gate capacitance and may damage the
circuit driving the fet (or cause the fet to turn on).

 

This is awesome michael. You're really helping to speed up my design phase! So, I've realized several things since yesterday and instead of posting about 10 schematics I want to look at a few examples first then post later.

And yes, I realize there's an issue at Vdd > 50V. In any case, the good news is that 350mA is great. 100mA will be great. The key question I need to answer relates to duty cycle. If I can get pulse profiles even half as nice as shown in your last plot, then I can get away with duty cycle close to 1/2. One pulse every 2ms is pretty much what I was hoping for.

Any chance you can show a plot at Vdd = 24V? No need and no hurry. I hope to have my simulation running soon.

 

Here's Vdd at 24 volts. I've added some possible? 3.3 volt drive interface(s).

 

Thanks michael! BTW, I'm making a lot of improvements based on other suggestions and will simulate them soon.

Your latest plot gives me hope that I can pulse once every 1 ms in some short bursts. That would be much better than expected!

 

Check out this link. You helped me in a big way to get here. Thanks Michael!

https://tinyurl.com/y776hb7y

 

Check out this link. You helped me in a big way to get here. Thanks Michael!

https://tinyurl.com/y776hb7y

This doesn't work, because at shutoff the V drop across the diodes is enormous. Still working on this.

 

600 volts!

 

Awesome! Looking forward to showing you what I ended up with. H-bridge rather than this kind of half-bridge, coil below 10mH and 20 ohms. Imagine that at 600V!

As it is I'll probably approach 120V. This will become a very dangerous device with any magnets (or iron) nearby.

Here's the thread that I created then followed to get some great answers. Check it out ...

https://electronics.stackexchange.c...needed-to-protect-these-mosfets-from-back-emf

 

Awesome! Looking forward to showing you what I ended up with. H-bridge rather than this kind of half-bridge, coil below 10mH and 20 ohms. Imagine that at 600V!

As it is I'll probably approach 120V. This will become a very dangerous device with any magnets (or iron) nearby.

Here's the thread that I created then followed to get some great answers. Check it out ...

https://electronics.stackexchange.c...needed-to-protect-these-mosfets-from-back-emf

Ha. I didn't see what you were doing. Yep, I saw something closer to 1.4kV actually:-( Here's why ....

We typically think of back emf from the coil. I did anyhow and got that wrong. The back emf occurs right at the two drains. Both of them. One stops conducting immediately and the other starts conducting immediately. In other words, current goes from 150mA to 0mA at one drain within nanosecs and goes from 0mA to approx 150mA at the other within nanosecs. That spike is mitigated by the reverse diode of the opposite FET normally. With my (ill-advised) diodes there is a tiny reverse current which causes an enormous voltage drop across one of the diodes. The drain closest to that diode sees that voltage and of course will be destroyed immediately.

 

600 volts!

View attachment 226013

I see you have zeners there. Hmm ... I'm actually not sure why the spike is so large in that case. Because the back emf at the zeners is enormous during that ultra fast current reversal?

 

They aren't zeners. The 1N5159 is a schottky diode (and way to low
in voltage). Schottky diodes are faster and lower drop than regular
Si diodes. This was supposed to be a simulation of your #32 circuit.

PS: Also looking at single supply and H bridge before your post on them..

 

> We typically think of back emf from the coil. I did anyhow and got
> that wrong.

That's why my 2 cent mental inductor model says that the current in
an inductor at supply switch off does not change and the voltage on
the coil is whatever it takes to maintain that current (for 0 seconds,
it's immediately decreasing after time 0).

 

> We typically think of back emf from the coil. I did anyhow and got
> that wrong.

That's why my 2 cent mental inductor model says that the current in
an inductor at supply switch off does not change and the voltage on
the coil is whatever it takes to maintain that current (for 0 seconds,
it's immediately decreasing after time 0).

Right. I just knew that the ALL the issues and concerns are completely back EMF related. I just didn't stop to think long enough to realize that it's happening right at the drains rather than the coil. My apologies.