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That looks interesting. I will read it. Thanks for sharing!
Please help! Generating Composite video signals from scratch
- Thread starter PauloConstantino
- Start date
Can I make oscillators with not gates resistors and capacitors for this project? Would them be too unstable? What kind of digital oscillators is best for this please?
No matter how precise the R-C components are, the transition levels in the gates will drift too much with temperature for reasonable accuracy. Depending on the monitor, it might not matter, but you won't know until it is all built. The classic sync generator is a crystal oscillator (4.43 MHz for mono-PAL) and some dividers. National Semiconductor and others made single-chip sync generators in the 80's. Another approach in an early timebase corrector was to have a counter drive an EPROM. You can grow one in a CPLD. None of the circuits are difficult, just messy.
ak
Thank you. Do you think I can remove the serrations from the sync for a start ? Can I make Vsync just a single long pulse instead of multiple short pulses? Would that work with a CRT? And also remove the equalizing pulses? If I use a 4MHz crystal, and then divide it by 128 to get 31.25KHz, is this ok ? Should I use a binary counter and take the 8th digit as my output ?
I wish I could do something simple and just see an image for a start. And then later I could redesign the circuit. It's so hard to try to do things when you were not the original creator. I built a complete cpu in a few days from my mind, but this composite video thing is driving me nuts!
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I remember using this book for some TV video circuits long ago. I may have used the discrete output (4-15) in my old 8080 S100 adapter for video generation.
http://www.tinaja.com/ebooks/TVTcb.pdf
http://www.tinaja.com/ebooks/TVTcb.pdf
I have this book. I find that it doesn't give me what I need. It's too specific for a typewriter and I am doing something different....
Hi,
You could start with a set of counters that reset after you get to the bottom line.
If the counters are driven by the main oscillator at the second stage instead of the first then you can set bit 0 to a zero for the even lines and to a 1 for the odd lines. Your counters might address a Ram or Rom to find out which 'pixels' get turned on and which dont. That is assuming you are generating simple digital patterns which you should probably start with anyway.
You could start with a set of counters that reset after you get to the bottom line.
If the counters are driven by the main oscillator at the second stage instead of the first then you can set bit 0 to a zero for the even lines and to a 1 for the odd lines. Your counters might address a Ram or Rom to find out which 'pixels' get turned on and which dont. That is assuming you are generating simple digital patterns which you should probably start with anyway.
It is in parts but chapter 8 (television interface) has some good general video interface information. I took some of the circuits and combined them with my own to make a pretty nice for the time character display with a graphics overlay using a few transistors, some CMOS with TLL clock drivers using that information.
I was having look at the picture I posted earlier, and I "noticed something":
it says we need equalizing pulses because we are doing interlace, that is, the last ,line must be half its width. So we insert an equalizing pulse, which takes half a line, and sends the beam to the left. I can understand this, however, why do they go ahead and add even more equalizing pulses? Why isn't just one ok ? And they also add them after the vsyn pulses. Why would that be? It seems they add equalizers in order to add lots of hsync pulses, but there are hsync pulses at the beginning of every line anyway.
I suffer from being too obsessed with understanding things too deeply!
it says we need equalizing pulses because we are doing interlace, that is, the last ,line must be half its width. So we insert an equalizing pulse, which takes half a line, and sends the beam to the left. I can understand this, however, why do they go ahead and add even more equalizing pulses? Why isn't just one ok ? And they also add them after the vsyn pulses. Why would that be? It seems they add equalizers in order to add lots of hsync pulses, but there are hsync pulses at the beginning of every line anyway.
I suffer from being too obsessed with understanding things too deeply!
It's been some time since I've worked with this stuff but you have to look at this from the standpoint of a voltage integration circuit rise/fall times and vertical sync trigger points.
It's been some time since I've worked with this stuff but you have to look at this from the standpoint of a voltage integration circuit rise/fall times and vertical sync trigger points.
The first and last images have it all inverted, why ?
I been thinking about designing a state machine in hardware to generate these signals.
I started drawing the ASM for it.
It starts with State0, and outputs a VSYNC_START bit, then goes to State1, called SYNC_WAIT, and in this state it waits for the VSYNC to finish, then when it is done, it goes to State3 where it outputs HSYNC_START, and then waits for each HSYNC to be done, then writes the video data, and then goes back to State0.
However, the waiting states themselves will be connected to other state machines, that actually generate the signals.
Now for the VSYNC machine. It starts at State0, where it is waiting for the VSYNC_START signal. Once the VSYNC_START signal is high, then this machine displays the equalizing pulses for a few clock cycles (half a line period). Once this is done, then it outputs the Vsync pulses, and then the final equalizing pulses. Once this is done then this machine outputs VSYNC_DONE signal.
The same applies to the HSYNC state machine.
How does this sound ?
I started drawing the ASM for it.
It starts with State0, and outputs a VSYNC_START bit, then goes to State1, called SYNC_WAIT, and in this state it waits for the VSYNC to finish, then when it is done, it goes to State3 where it outputs HSYNC_START, and then waits for each HSYNC to be done, then writes the video data, and then goes back to State0.
However, the waiting states themselves will be connected to other state machines, that actually generate the signals.
Now for the VSYNC machine. It starts at State0, where it is waiting for the VSYNC_START signal. Once the VSYNC_START signal is high, then this machine displays the equalizing pulses for a few clock cycles (half a line period). Once this is done, then it outputs the Vsync pulses, and then the final equalizing pulses. Once this is done then this machine outputs VSYNC_DONE signal.
The same applies to the HSYNC state machine.
How does this sound ?
A few quick comments...
The drawing showing the diagonal lines is greatly exaggerated. The slope of the line is only from one line to the next -- about one line spacing or 1/600(?) of the height of the screen.
Even though it is US TV standard, you may want to check out Don Lancaster's TV Typewriter Cookbook. (Mentioned in previous posts.)
Also check out Appendix B A Color TV Primer for the E.E in the 1999 National Semiconductor Linear Applications handbook. The PDF is 399MB.
I have not managed to view the much smaller .gz version.
https://archive.org/details/NationalSemiconductor-LinearApplicationsDatabook1986OCR
There are both equalizing pulses and serration pulses. I can't remember off the top of my head which is which. One of these is used to keep the horizontal oscillator in sync during the vertical retrace. These pulses are needed even if non-interlaced video is generated.
If you leave out these horizontal "sync" pulses during the vertical interval then the image will have curved vertical lines because the horizontal oscillator will have lost lock and drifted during the vertical retrace.
The drawing showing the diagonal lines is greatly exaggerated. The slope of the line is only from one line to the next -- about one line spacing or 1/600(?) of the height of the screen.
Even though it is US TV standard, you may want to check out Don Lancaster's TV Typewriter Cookbook. (Mentioned in previous posts.)
Also check out Appendix B A Color TV Primer for the E.E in the 1999 National Semiconductor Linear Applications handbook. The PDF is 399MB.
I have not managed to view the much smaller .gz version.https://archive.org/details/NationalSemiconductor-LinearApplicationsDatabook1986OCR
There are both equalizing pulses and serration pulses. I can't remember off the top of my head which is which. One of these is used to keep the horizontal oscillator in sync during the vertical retrace. These pulses are needed even if non-interlaced video is generated.
If you leave out these horizontal "sync" pulses during the vertical interval then the image will have curved vertical lines because the horizontal oscillator will have lost lock and drifted during the vertical retrace.
In the US, the video is transmitted "upside down". This makes the sync pulses the largest amplitude and the white level the smallest amplitude. I think video is biggest since you never want to lose sync even when receiving a poor signal. Similarly, the black is bigger than white to make noise in the video less visible.
If I am remembering wrong, I am sure someone will correct me.
p.s. I wish the US digital standard was as well designed in this respect as the old, and in many ways better, analog standard.
A few quick comments...
The drawing showing the diagonal lines is greatly exaggerated. The slope of the line is only from one line to the next -- about one line spacing or 1/600(?) of the height of the screen.
Even though it is US TV standard, you may want to check out Don Lancaster's TV Typewriter Cookbook. (Mentioned in previous posts.)
Also check out Appendix B A Color TV Primer for the E.E in the 1999 National Semiconductor Linear Applications handbook. The PDF is 399MB.
https://archive.org/details/NationalSemiconductor-LinearApplicationsDatabook1986OCR
There are both equalizing pulses and serration pulses. I can't remember off the top of my head which is which. One of these is used to keep the horizontal oscillator in sync during the vertical retrace. These pulses are needed even if non-interlaced video is generated.
If you leave out these horizontal "sync" pulses during the vertical interval then the image will have curved vertical lines because the horizontal oscillator will have lost lock and drifted during the vertical retrace.
That ebook looks amazing! A lifetime of learning. What is it about? Analogue electronics? I am downloading it right now!
That pretty much sums it up.
There probably isn't much use for interlaced outside TV.
For the UK system; its pretty involved - the vertical sync is produced by "equalisation pulses" in the horizontal pulse train. Horizontal pulses that exceed the viewable screen have different widths - the on time is integrated to make the vertical pulses.
The college course told me there was an; "interlace diode" - but I never had to sort out an interlace fault, so I didn't spend much time expanding my studies on that point.
There used to be chips that did it all for you - I vaguely remember that the 6845 video generator could be configured for interlaced or progressive scan. There were probably other MCU support chip families with the same capability.
Philips and Ferranti did various video generator chips that were handy for cameras and TV pattern generators etc - but I doubt any are still available.
Actually it was 3 or maybe 4 resistors and a 2n3904. The entire circuit including the battery was built into a couple of Atari 2600 paddles that had pots in them.
I don't think I have any digital documentation available on this project.
Actually it was 3 or maybe 4 resistors and a 2n3904. The entire circuit including the battery was built into a couple of Atari 2600 paddles that had pots in them.
I don't think I have any digital documentation available on this project.
Ricardo, help me generate the signals ? What kind of oscillator should I build? I read in a tutorial that there is a stable oscillator that can be made with NOT gates. I am thinking of building state machines to control the syncs. Is it easier to use just counters?
I am also thinking of using a simple binary counter, and then using and and or Gates to see where the counter is, and then display the sync signals accordingly. Does that work ?
The 2-inverter crystal oscillator is good enough for this application. The TV dos not care about a fraction of a percent error in video frequencies.
In the US I would start with a 14.31818MHz crystal. This is 4 times the color burst frequency in NTSC video. I don't know what the equivalent frequency is in the PAL system. I vaguely remember using something like 20.5 MHz.
Found it -- see the PDF -- actually 2.5625 MHz. I think I started with the 20.5 MHz and divided it by 8 to get the clock for the ZNA134. The 20.5 MHz was used for the pixel clock. You probably don't need that many pixels on a TV line.
