# LTspice inconsistent MOSFET gate driver behavior

#### Mohammed SETTI

Joined Mar 6, 2018
10
Hello,
I am working on a 7-level power micro-inverter which composed mainly by power MOSFETs. These logic-level MOSFETs (IRLZ24NS) are driven by separate photovoltaic gate drivers with integrated fast turn-off (Broadcom ACPL-K30T). The problem comes when I try to simulate the circuit and compare the results with those obtained by experiments. The circuit topology with relevant signals looks like this:

As you can see, the gate-to-source voltage of the MOSFET M11 (V(g)-V(s)) at time starting from 11.68ms should be near to zero volts and not 2.31V, because the charge of the parasitic capacitors (Cgd and Cgs) will be discharged through the gate driver circuitry. This assertion was verified by breadboarding and gives the following result:

Noting that during my experiment I was using available Panasonic AVP1122 gate drivers instead of Broadcom ACPL-K30T which has comparative capabilities. However, I guess that problem comes from the ACPL-K30T SPICE model itself, I've tried to decipher it but didn't succeed, so I ask you SPICE gurus to help me understand the reasons behind this issue. The SPICE code is given below:

Avago ACPL-K30T Spice Macromodel:
* ACPL-K30T  Spice Macromodel
.subckt ACPL-K30T AN CA VOUT- VOUT+
E1 N002 CA N014 N016 {CTR}
XX1 AN CA N016 N014 vbu
XX2 N002 CA N017 N015 pdnoc
XX3 N002 CA N008 N017 pdnoc
XX4 N002 CA N015 N013 pdnoc
XX5 N002 CA N013 N012 pdnoc
XX6 N002 CA N012 N010 pdnoc
XX7 N002 CA N010 N007 pdnoc
XX8 N002 CA N007 N004 pdnoc
XX9 N002 CA N004 N003 pdnoc
XX10 N002 CA N003 P001 pdnoc
XX11 N002 CA P002 P003 pdnoc
E2 N011 VOUT- N008 N001 1
R2 N009 N011 1k
D1 VOUT- N001 D
D2 N008 VOUT+ D
E3 N009 N006 N008 VOUT- 1
Q1 VOUT+ N006 N005 0 NPN
R3 VOUT- N005 3k
C1 VOUT- N009 37n
XX12 N002 CA P003 N001 pdnoc
XX13 N002 CA P001 P002 pdnoc
C2 VOUT- VOUT+ 100p
.param CTR=0.083
.ends ACPL-K30T

.subckt vbu AN CA LOPN LOPP
RSERIES AN 5 5
DELECT 5 CA VBUNOR
ELED 6 LOPN 5 CA 1
DOPTIC 6 8 VBUNORC
FPHOTO LOPN 3 VSENSE 1
VSENSE 8 LOPN 0
RL 3 LOPN 0.1
EOUT LOPP LOPN 3 LOPN 60
VSIM LOPN CA 0
Rnl 6 N001 5k
Vnl N002 LOPN 0
Fnl LOPN LOPN Vnl 1
Dsw N001 N002 DSW
.model DSW D Is=1e-4
.model VBUNOR D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
.model VBUNORC D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=0 VJ=.75 M=.3333 FC=.5 TT=0
.ends vbu

.subckt pdnoc LOPP LOPN AN CA
D1 AN CA PDC
G1 CA AN LOPP LOPN 0.0010
.model PDC D IS=1E-14 N=1.5 CJO=0p M=0.95 VJ=0.75 ISR=100.0E-12 BV=100 TT=5E-9
.ends pdnoc

.model D D
.model NPN NPN
.model PNP PNP

Thank you

#### ronsimpson

Joined Oct 7, 2019
2,062

#### Irving

Joined Jan 30, 2016
2,666
How comparable are the AVP1122 to the ACPL-KT30? Are you truely comparing apples with apples? Some ideas to focus on the problem:

How about breadboarding an AVP1122 in isolation and comparing that to the same Spice simulation?

Also, is there a Spice model for the AVP1122?

Looking at the Spice code, it seems, without diving in too deep, they use a complex piece-wise transfer generation to model what I suspect is some tricky non-linear behavoir. Analysing it might be time consuming but not necessarily enlightening...

Last edited:

#### Mohammed SETTI

Joined Mar 6, 2018
10
Here is the *.asc file with the PWL gating signal files.

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#### Mohammed SETTI

Joined Mar 6, 2018
10
How comparable are the AVP1122 to the ACPL-KT30? Are you truely comparing apples with apples? Some ideas to focus on the problem:

How about breadboarding an AVP1122 in isolation and comparing that to the same Spice simulation?

Also, is there a Spice model for the AVP1122?

Looking at the Spice code, it seems, without diving in too deep, they use a complex piece-wise transfer generation to model what I suspect is some tricky non-linear behavoir. Analysing it might be time consuming but not necessarily enlightening...
Yes both are based on the same principle and btw accomplishing the same functionality.
I cannot find any SPICE model for the AVP1122.

#### ronsimpson

Joined Oct 7, 2019
2,062
The gate driver can only out put uAs. (4 to 10uA???) Try putting a resistor G-S on the mosfets. Maybe 5mega ohm.

I looked inside the IC and it looks to me that the "pull down, turn off circuit" only works when there is voltage and quits when the voltage is low. I think the IC pulls down, sees the voltage drop and stops. The G-D capacitance in the MOSFET pulls the Gate high but not enough to turn the turn-off circuit back on.

#### Mohammed SETTI

Joined Mar 6, 2018
10
The gate driver can only out put uAs. (4 to 10uA???) Try putting a resistor G-S on the mosfets. Maybe 5mega ohm.

I looked inside the IC and it looks to me that the "pull down, turn off circuit" only works when there is voltage and quits when the voltage is low. I think the IC pulls down, sees the voltage drop and stops. The G-D capacitance in the MOSFET pulls the Gate high but not enough to turn the turn-off circuit back on.
Yes since the gate driver doesn't require any external power source it sources current in micro-amps but the logic-level MOSFET is chosen with small Qg.
My question is why does the IC stop to pull down the gate voltage? Is it a normal/expected behavior?
I read somewhere in the application note the following statement:

Some events may cause the relay to unintentionally turn on. One example is when a fast transient current spikes across the drains of the MOSFET, charging the MOSFET gates through the parasitic capacitance. For the ACPL-K30T driver, the internal circuitry clamps the photovoltaic driver output below the minimum MOSFET threshold, VTH. This keeps the ACPL-K30T driver in an off state and prevents the device from unintentionally turning on. Figure (attached) shows the I-V curve of the ACPL-K30T output when the LED is off.
But the voltage is always clamped to less than 1 volt!

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#### Irving

Joined Jan 30, 2016
2,666
Yes both are based on the same principle and btw accomplishing the same functionality.
I cannot find any SPICE model for the AVP1122.
Yes, similar principles. but significant differences in terms of speed and load driving capability.

#### Mohammed SETTI

Joined Mar 6, 2018
10
Yes, similar principles. but significant differences in terms of speed and load driving capability.
Ofcourse
Yes, similar principles. but significant differences in terms of speed and load driving capability.
Of course there are always differences in capabilities between any different devices but what is interested here is why the turn off circuitry behaves as such. Typically the gate voltage should be at most less that the MOSFET threshold voltage. The application note of the gate driver states that the voltage won't exceed 1 volt which would be acceptable and doesn't unintentionally turn on the MOSFET

#### Irving

Joined Jan 30, 2016
2,666
Well, its not the Spice model per se that's the issue... Here it is driving the test configuration of 10Meg || 1nF, and driving a single IRLZ24N MOSFET, and driving another logicFET... The issue seems to be the IRLZ24N...

#### Mohammed SETTI

Joined Mar 6, 2018
10
Well, its not the Spice model per se that's the issue... Here it is driving the test configuration of 10Meg || 1nF, and driving a single IRLZ24N MOSFET, and driving another logicFET... The issue seems to be the IRLZ24N...

View attachment 266573
Thank you for your test! Before I get into this inverter simulation I test every single component in the same way as you did. The driver with the MOSFET works perfectly in both low- and high-side modes. But without changing aggressively the voltage at the drain. I think the problem comes from the driver turn-off circuitry under off state since it is unable to clamp the gate voltage to zero caused by the Miller capacitance Cgd.

#### ronsimpson

Joined Oct 7, 2019
2,062
I think the problem comes from the driver turn-off circuitry under off state since it is unable to clamp the gate voltage to zero caused by the Miller capacitance Cgd.
Agree

#### Irving

Joined Jan 30, 2016
2,666
Thank you for your test! Before I get into this inverter simulation I test every single component in the same way as you did. The driver with the MOSFET works perfectly in both low- and high-side modes. But without changing aggressively the voltage at the drain. I think the problem comes from the driver turn-off circuitry under off state since it is unable to clamp the gate voltage to zero caused by the Miller capacitance Cgd.
That may be so, but is that a reflection of reality or an issue with the IRLZ24NS spice model... Using the IRLZ44N spice model, a closely similar part (but with a higher gate charge) I use extensively both in simulation and in real life, your simulation behaves more as expected....

#### Mohammed SETTI

Joined Mar 6, 2018
10
That may be so, but is that a reflection of reality or an issue with the IRLZ24NS spice model... Using the IRLZ44N spice model, a closely similar part (but with a higher gate charge) I use extensively both in simulation and in real life, your simulation behaves more as expected....

View attachment 266610
Thank you again for your effort! I've tested this MOSFET spice model and also the IRLZ34N part but the output v(s) is far from that obtained by experiments. I think the only logical fix is to add a resistor of about 1Meg in parallel with a tiny capacitor of 1-20pF between the gate and the source in order to simulate the x10 oscilloscope probe.

#### Irving

Joined Jan 30, 2016
2,666
add a resistor of about 1Meg in parallel with a tiny capacitor of 1-20pF between the gate and the source in order to simulate the x10 oscilloscope probe.
x10 probe would be 10Meg || 15-20p approx