I am not that experienced in using LTSpice especially for modelling for Lithium batteries or capacitors to test out a switched capacitor equalising circuits. Please, kindly guide me.

 

It likely can simulate it, but we need to see the circuit before we can give a definitive answer.

 

It likely can simulate it, but we need to see the circuit before we can give a definitive answer.

Can I give a sketch?

 

Can I give a sketch?

If it's clear and organized (not jumbled) with orthogonal wire connections and with component values.

 

 

L and C are 2.2uH and 10uF. In place of cells, use a supercapacitors SC1 = 345 F, SC2 = 300 F, and SC3 = 276 F, respectively, and the voltages were initially set to 2.00, 2.30, and 2.50 V.

 

Okay.
So what exactly is this circuit supposed to do, and what is the timing of the switches?

 

Okay.
So what exactly is this circuit supposed to do, and what is the timing of the switches?

It is supposed to balance all the capacitor voltages. The switching frequency is 34kHz.

 

Have you picked out part numbers for the MOSFETs, or are you just interested in seeing how it works?

 

Have you picked out part numbers for the MOSFETs, or are you just interested in seeing how it works?

I'm interested to see how it works

 

In addition, I would modify the simulation to suit my need. So, I would want to understand how to simulate the original work first. Thanks

 

? at #5 "the highest voltage > rated voltage" ← sounds like a fault condition ?
? what would be the peak current load for D₂ʙ? , ?D₂ᴀ ← those things have reverse current and may get faulted to a short . . .

otherwise

your supposedly limitting LC "charge transfer buffer" has a reactance = if the coil is still "busy" ripping the charge from the source it won't transfer it to lower voltage super cap . . . i mean you might want to change the concept

also

while simulating large caps at LTspice may induce ULF oscillations ← not comfortable to be tracked at transient run cos the transient run is diferential integration

► you can swap the switching mosfets with voltage controlled switches . . . for idealized circuit responce . . .

. . . if the caps had different I&O ports you might try something that allows simultaneous transfer start (← a speculation)
. . . IF the drains of consequential switches (S₁₃ , S₂₁) S-caps are shorted ← induces you have a series stack of S-caps & you CAN NOT have 2 of them connected to your "charge transfer buffer" at the same time window ← and they likely need a signifficant delay in between that
▲ you still may want to rework your concept

https://www.ti.com/document-viewer/lit/html/SSZT144

also excessive currents (energy) at S-caps induces switching artefacts ~ which even if sucessfully damped would make the simulation a painful waiting
you likely like to reduce your S-caps to milli-F range and perhaps limit the currents . . .

 

? at #5 "the highest voltage > rated voltage" ← sounds like a fault condition ?
? what would be the peak current load for D₂ʙ? , ?D₂ᴀ ← those things have reverse current and may get faulted to a short . . .

otherwise

your supposedly limitting LC "charge transfer buffer" has a reactance = if the coil is still "busy" ripping the charge from the source it won't transfer it to lower voltage super cap . . . i mean you might want to change the concept

also

while simulating large caps at LTspice may induce ULF oscillations ← not comfortable to be tracked at transient run cos the transient run is diferential integration

► you can swap the switching mosfets with voltage controlled switches . . . for idealized circuit responce . . .

. . . if the caps had different I&O ports you might try something that allows simultaneous transfer start (← a speculation)
. . . IF the drains of consequential switches (S₁₃ , S₂₁) S-caps are shorted ← induces you have a series stack of S-caps & you CAN NOT have 2 of them connected to your "charge transfer buffer" at the same time window ← and they likely need a signifficant delay in between that
▲ you still may want to rework your concept

https://www.ti.com/document-viewer/lit/html/SSZT144

also excessive currents (energy) at S-caps induces switching artefacts ~ which even if sucessfully damped would make the simulation a painful waiting
you likely like to reduce your S-caps to milli-F range and perhaps limit the currents . . .

View attachment 367754

The rated voltage is 2.5 V. I will check the reason for using diodes. This is an academic work that needs improvement.

 

What is the purpose of L and C?
If you are trying to equalize the voltages with high efficiency, I don't see how that can work (?).

 

What is the purpose of L and C?
If you are trying to equalize the voltages with high efficiency, I don't see how that can work (?).

L and C are series resonant tank.
This is the whole idea. One supercapacitor transfer its charge to the tank based on the decision in the flow chart. The charge get transfers to other with low supercapacitor based on the flow chart. Then, the corresponding switches get activated.

 

Okay.
So what exactly is this circuit supposed to do, and what is the timing of the switches?

It's an active balancer. Basically it transfers energy from the highest voltage source to the lowest. The one I built doesn't have a resonant tank like this though, it's more like a buck converter where one set of switches select/switch the source cell and another set pass through to the destination cell. When the differential reaches a small enough value, system moves on to the next suitable pair.

 

It's an active balancer. Basically it transfers energy from the highest voltage source to the lowest. The one I built doesn't have a resonant tank like this though, it's more like a buck converter where one set of switches select/switch the source cell and another set pass through to the destination cell. When the differential reaches a small enough value, system moves on to the next suitable pair.

Exactly, I just need to understand how to simulate it. Then, I would develop my own genuity.

 

Exactly, I just need to understand how to simulate it. Then, I would develop my own genuity.

? https://groups.io/g/LTspice/ ← try at

. . . it is that small inductors with fast switching and large electrical capacities
are prone to HF/UHF oscillations
also the spice tends to fail it's energy conservation at fast di/dt dv/dt cases
--means--
your thing is demanding expert level task to cope with . . .