LtSpice - Inconsistent simulation of identical circuits?

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Hypatia's Protege

Joined Mar 1, 2015
3,226
Kind friends.

Please note that the PSU circuit represented in the attached schematic and image files is comprised of two identical circuits connected for 'complementary' (i.e. 'split polarity') output.

My question -- As simulated: |Ek| - |Ea| = 16.887V -- when one would expect |Ek|=|Ea|:confused:
Granted! 1/30'th of 1% isn't much -- even so, one wishes to understand 'the ways of Spice':cool:

Perhaps component tolerance is simulated by default?:confused:

Many advance thanks for any insight/info!:)

Best regards
HP:)

PS -- Re: the attached image -- please note that although the cursors are occulting the traces -- I assure you they are there!:D

MazPsuSim.png
 

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jpanhalt

Joined Jan 18, 2008
10,221
Interesting. For 3 runs, I got 2.281 V (0.00306%), 1.24 V, and 0.26 V differences. The latter values were -75.58909 kV and 74.589351 kV. I wonder whether the cursor value is reading pixels on my screen versus the result of a mathematical calculation? If it is actually reading the screen, I am surprised it is that good.

Here is a snippet of the positive voltage with cursor:
upload_2016-8-29_5-21-35.png

And of the negative cursor (magnifications are not identical):

upload_2016-8-29_5-24-21.png

The fine structure of the curves are very slightly different at the maxima. Although, at the normal viewing size, they appear to be identical. At the same time, one voltage's ripple may be increasing and the other decreasing. Measurement on the ripple might not be identical.

Do you get similar results with very high enlargements?

John
 

OBW0549

Joined Mar 2, 2015
3,546
Granted! 1/30'th of 1% isn't much -- even so, one wishes to understand 'the ways of Spice':cool:
SPICE does mysterious things like this from time to time. It is also not exact. You might try fiddling with the RELTOL option a bit to see if you can improve results.

Perhaps component tolerance is simulated by default?:confused:
No, it does not. SPICE only simulates component tolerances by performing multiple simulation runs, each with different component values according to your tolerance specifications, in a Monte Carlo analysis.
 

GopherT

Joined Nov 23, 2012
8,012
@Hypatia's Protege

You are looking at a single point in time, 10 mSec after simulation startup. Let it run longer to get to see if the error shrinks. Set starting values of the components instead of letting everything start at 0V. Expecting a stable system in 10 mSec on a 50kV system doesn't happen in real life, why should it happen in a simulation?

Spice uses Monte Carlo methods for simulation...
https://en.wikipedia.org/wiki/Monte_Carlo_method

You should have more precise answers after longer simulation time.
 
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Alec_t

Joined Sep 17, 2013
11,640
There's something that looks like random noise in the waveforms. Easiest to see if you add a behavioural voltage source whose output is the sum of the two waveforms.
 

MrAl

Joined Jun 17, 2014
7,803
Kind friends.

Please note that the PSU circuit represented in the attached schematic and image files is comprised of two identical circuits connected for 'complementary' (i.e. 'split polarity') output.

My question -- As simulated: |Ek| - |Ea| = 16.887V -- when one would expect |Ek|=|Ea|:confused:
Granted! 1/30'th of 1% isn't much -- even so, one wishes to understand 'the ways of Spice':cool:

Perhaps component tolerance is simulated by default?:confused:

Many advance thanks for any insight/info!:)

Best regards
HP:)

PS -- Re: the attached image -- please note that although the cursors are occulting the traces -- I assure you they are there!:D

View attachment 111165
Hello there,

It looks like it could be a simple phase delay in the calculation due to the step size.
For example, if we calculate two RC networks by hand for time increments of 0.1 second each, we have to do one before the other and so RC1 gets calculated at t=1.1 and is logged as a solution while RC2 still has it's value of 1.0, the old value. If it is displayed at t=1.1 the values will not be the same until RC2 is calculated if there is a calculation delay, and it is even possible that each network gets calculated at alternate sub steps, which would mean RC1 gets calculated at t=1.05 and RC2 gets calculated at t=1.10 seconds, then the results displayed for each.
Try setting the max step size much smaller like 1e-8 and see if there is a lower error.

It could also be the rounding method used, where they use the alternate random round method for binary values which is believed to produce lower distributed errors over a large number of calculations.
 

MrAl

Joined Jun 17, 2014
7,803
That does the trick. Here's what the sum looks like when max step = 1e-8 :-
View attachment 111182
The error is now down at the uV level after a few mS.
Hi,

Oh yes, very nice :)
I hope it didnt take too long to run with the smaller step size, that's the drawback although set within reason it gives better results simply because all the derivatives are naturally smoother, and wow, there must be a lot of derivatives in this circuit.

I would say that it could indicate a flaw in the adaptive step algorithm they use but then again the original accuracy wasnt that bad either...we just got very picky :)
 

MrAl

Joined Jun 17, 2014
7,803
Hello again,

Oh that's great, i guess :)

That might mean we could try to simulate one of those chaotic oscillators. I tried one and it didnt act chaotically but i think it was because the simulator was noiseless and a real circuit always has some noise.

I ran into a real life problem one time where the noise was very low so the design did not work because it depended on at least a small amount of noise. I had trouble convincing the designer because it looked good on paper.
 

KL7AJ

Joined Nov 4, 2008
2,225
Kind friends.

Please note that the PSU circuit represented in the attached schematic and image files is comprised of two identical circuits connected for 'complementary' (i.e. 'split polarity') output.

My question -- As simulated: |Ek| - |Ea| = 16.887V -- when one would expect |Ek|=|Ea|:confused:
Granted! 1/30'th of 1% isn't much -- even so, one wishes to understand 'the ways of Spice':cool:

Perhaps component tolerance is simulated by default?:confused:

Many advance thanks for any insight/info!:)

Best regards
HP:)

PS -- Re: the attached image -- please note that although the cursors are occulting the traces -- I assure you they are there!:D

View attachment 111165
I also discovered that LT Spice limits the Q of a simple LC tank circuit to a value of 1000. Not that there's any problem with this....other "manifestations" of SPICE will simply spit out a divide by zero error if you have infinite Q. I haven't been able to identify the limiting factor in LTspice....I presume a fixed finite resistance is incorporated into even "perfect" inductors....though this doesn't seem to show up on any of the library inductor properties.

Eric
 

OBW0549

Joined Mar 2, 2015
3,546
That might mean we could try to simulate one of those chaotic oscillators. I tried one and it didnt act chaotically but i think it was because the simulator was noiseless and a real circuit always has some noise.
Those noise sources would only be active during a .noise analysis, which is a special form of .ac analysis; they would not show up during a time-domain .tran analysis.

I ran into a real life problem one time where the noise was very low so the design did not work because it depended on at least a small amount of noise. I had trouble convincing the designer because it looked good on paper.
Been there, done that. I once worked on a product in which the clock oscillator for a CPU chip was built from a couple of TTL inverter gates, a crystal resonator, a couple of resistors and a capacitor. Crude but effective; it always started up and worked perfectly.

Until one day when we got a panicked call from Production: CPU cards were all passing their board-level tests, but when assembled into their card racks along with the voltage regulator card and RAM, ROM, ADCs, DACs, etc. they either wouldn't work at all or would mysteriously go several seconds or even minutes after power-up without working, then suddenly start oscillating, after which they worked fine.

The engineer responsible for the CPU card pulled his hair out for several days before finally tracking down the problem: the regulator card, based on a switching regulator, was too quiet! It seems Purchasing had begun buying filter capacitors for the regulator cards from a different manufacturer, and the new capacitors had a much lower ESR than the old ones, as well as much, MUCH lower equivalent series inductance. As a result, the tiny little voltage spikes that were normally on the regulator output were now about one-tenth the amplitude they had been previously.

And unbeknownst to the engineer, his oscillator circuit depended on those spikes to initiate oscillation. No spikes ==> dead CPU!
 

MrAl

Joined Jun 17, 2014
7,803
Hi again,

Interesting story. It's funny the things that can turn up as time goes by. Time is the greatest tester of them all :)

It's too bad then that LTS doesnt work in time domain for noise analysis, but maybe they have a separate noise source we can put into the circuit? Or maybe they allow a "rand" function in one of the function sources.
That's what i used in the past, but not for LT Spice yet.

LATER:
Ok rand works but will take a little fussing with to get a decent 'noise' signal.
 
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