Yes trying the same.
Apart from following Bordodynov's advice you could simulate parts of the circuit separately.can we reduce this? time.
Change the signal edges to 10 ns - PULSE(0 5 100u 10n 10n 10u 20u). This will speed up the score 1.5 times.Hi Bordodynov,
Thanks for reply and reminder. I missed that thread. I will try and confirm. As per your suggestion simple logic gates means do you suggest simple behavioral blocks ?
Thanks,
Amod
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