LT Spice for Digital circuit simulation

ericgibbs

Joined Jan 29, 2010
21,442
hi,
OK,
So your asc file should have .include Sol_Curr.txt statement added.
Place the text file in the same folder as the asc file.

Your text file format is not compatible with LTS

Label,,,,
TIME,CH1,CH2,CH3,CH4
-2.000000e+00,23.1719,-0.8125,27.0781,0.0065625
-1.996000e+00,23.1797,-0.890625,27.1172,0.00617187
-1.992000e+00,23.1562,-0.9375,27.0938,0.00625
-1.988000e+00,23.1797,-0.898438,27.1172,0.00585938
.......................

The text file must have an Header like this example,[ time, value]
.subckt BV_PT0_100 outp outn inp inn
B1 outp outn V =Table(V(inp,inn)
+ ,0,100
+ ,1,100.391
+ ,2,100.781
+ ,3,101.172
+ ,4,101.562
+ ,5,101.953
+ ,6,102.343
+ ,7,102.733
 

Thread Starter

amod.mujumdar

Joined Apr 2, 2019
34
Hi ,

I am simulating complete simulation of design. It completed simulation .RAW file generated. However after that it crashed. Now using .raw file ca I get traces or shall I simulate again?
Further sometimes while simulating it stops refreshing % value but in menu it show running but no simulation updated ? here it looks like simulation is stopped. Can we start form point where it stops / or shall I start it again. ?

Pl. clarify and suggest.

Is there any command to be set to speed up simulation ?

Amod
 

Bordodynov

Joined May 20, 2015
3,431
You have learned nothing from my example. And you do everything to slow down the simulation process. Why are you doing pulse fronts 1 ns? Also, the simulation process is dramatically accelerated if you reduce the amount of necessary memory and you'll remember, only the necessary nodes of the circuit. The fact is that you are not using simple logic elements, but subcircuits in which there are many elements and nodes of the circuit inside. As a result, the expanded scheme is very large - many nodes of the scheme. And it makes little sense to memorize them. Use the command ".Save the list of necessary nodes"
 

Thread Starter

amod.mujumdar

Joined Apr 2, 2019
34
Hi Bordodynov,

Thanks for reply and reminder. I missed that thread. I will try and confirm. As per your suggestion simple logic gates means do you suggest simple behavioral blocks ?

Thanks,
Amod
 

Bordodynov

Joined May 20, 2015
3,431
Hi Bordodynov,

Thanks for reply and reminder. I missed that thread. I will try and confirm. As per your suggestion simple logic gates means do you suggest simple behavioral blocks ?

Thanks,
Amod
Change the signal edges to 10 ns - PULSE(0 5 100u 10n 10n 10u 20u). This will speed up the score 1.5 times.
Add a directive to the schema (using S)
.save V (TMR_CNT_ENA) v (+ SLOPE) v (~ POR) v (CLK) v (SOL_IFB) v (END_CYCL) v (CLK) v (~ LD_TMRS) v (OCUR)
Add more if I lost something.
 

Thread Starter

amod.mujumdar

Joined Apr 2, 2019
34
Hi All,

Thank you for your help. With your guidelines I could simulate many things. Now one question that If we are using 74HC14 sch mitt trigger inverter. Now this has NXP and Texas Instrument parts

NXP - 74HC14PW VT- = 1.4V and VT+ 2.38V
TI - SN74HC14 VT- 1.6V and VT+ = 2.5V

Now in simulation for parts can we set these threshold values ?

Pl. suggest.

Thanks,
Amod
 
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