Hi,
In (H)SPICE, I have a block of logic gates which requires a 16 bit input and have one bit output which is activated when the computation in the logic block is finished.
I want to feed the logic block with a set of input vectors (originally they are in a file with one 16 bit number for each line, but I've made a script to transform my input into a piece wise linear input if needed). The problem is that I need to change the input vector when the signal "end of computation" of my logic block is activated. I can't predict the timing when my computation is finished (I'm doing a monte carlo simulation and each time the timing of the computation can change quite a lot).
Does anyone know how to change the input vector when such a signal is activated? I can't use PWL since it requires precise timing of when my computation is finished. I've tried to feed my input into a gated latch, but it doesn't work for a big number of input vector.
Thank you!
In (H)SPICE, I have a block of logic gates which requires a 16 bit input and have one bit output which is activated when the computation in the logic block is finished.
I want to feed the logic block with a set of input vectors (originally they are in a file with one 16 bit number for each line, but I've made a script to transform my input into a piece wise linear input if needed). The problem is that I need to change the input vector when the signal "end of computation" of my logic block is activated. I can't predict the timing when my computation is finished (I'm doing a monte carlo simulation and each time the timing of the computation can change quite a lot).
Does anyone know how to change the input vector when such a signal is activated? I can't use PWL since it requires precise timing of when my computation is finished. I've tried to feed my input into a gated latch, but it doesn't work for a big number of input vector.
Thank you!
