I am debugging a DC-DC full-bridge converter where the power stage and gate drive operate correctly in open-loop, but the gate driver ICs repeatedly fail when the control loop is closed. I am looking for insights into what mechanisms could cause this behavior.

System Overview
1. Topology: Full-bridge DC-DC converter
2. Controller: UC3875
3. Gate Driver: ADuM4221 (isolated)
4. Switching frequency:
a. Initially 400 kHz
b. Reduced to 100 kHz during troubleshooting
5. Input: 28 V
6. Output: 42-24 V (open-loop observed)

Observed Behavior
➔ In open-loop operation (Max duty, no feedback):
◆ Converter operates normally
◆ Gate drivers draw expected current (~5 mA)
◆ No abnormal heating or current spikes observed

➔ When feedback loop is closed:
◆ Audible noise from inductor appears
◆ Output initially looks correct, then degrades within seconds
◆ Gate driver supply current increases abnormally
◆ One or both ADuM4221 gate drivers eventually fail

➔ When powered again after failure, the drivers is no longer functioning

Troubleshooting Performed
➔ Verified PCB layout and gate routing (no shorts or coupling issues found)
➔ Replaced all MOSFETs and gate driver ICs multiple times
➔ Reduced bootstrap capacitor from 10 μF to 1 μF
➔ Replaced bootstrap diodes with Schottky diodes
➔ Added low-value RBOOT resistor (~1 Ω) before bootstrap capacitor
➔ Introduced dead time (~350-450 ns) between complementary switches
➔ Confirmed controller IC remains functional
➔ Verified that the same hardware works repeatedly in open-loop

What failure mechanisms could cause gate driver ICs to fail only during closed-loop operation, while remaining stable in open-loop?I would appreciate guidance on what to instrument or measure next (e.g., driver VDD, gate-source waveforms, shutdown behavior) and design changes typically recommended to protect gate drivers in this scenario.

 

Without a circuit diagram I can't say much.
From "audible noise from inductor" my guess is that your feedback loop is unstable

 

Thank you for the response.

As suggested, I’m attaching the relevant circuit images with this post specifically the output filter section and the PWM controller.
One clarification regarding the audible noise: out of three closed-loop startup attempts, only one instance produced audible noise from the transformer. In the other two attempts, there was no audible noise at all, and the gate driver IC failed immediately at turn-on.

 

Here are some things to look at.
Many Gate Drivers cannot go to 100% on or 0% on. (or even more than 90%) This is a problem at power up or full load.
Many Gate Drivers have an under voltage turn off function. At power up the supply voltage might dip and turn off the Drivers.

Replaced bootstrap diodes with Schottky diodes

I cannot see enough of the schematic so know what is happening. Boot strap Drivers are known for problems at start up.
Where are they on the schematic?
Try increasing the "soft start" capacitor.

 

Thank you for your response. The bootstrap circuit details are attached with this message. As you mentioned, many gate drivers cannot achieve 100% (or even >90%) duty cycle due to bootstrap limitations, and the undervoltage lockout (UVLO) may cause the drivers to turn off during supply dips at startup or full load.

In our case the system operates reliably in open-loop without any driver failure. Could you kindly help us understand why the same bootstrap and supply conditions would cause gate driver malfunction only when the control loop is closed?

 

Do the MOSFETs fail, or just the gate drivers?

 

Do the MOSFETs fail, or just the gate drivers?

Out of the three closed-loop test attempts, the MOSFET failed once. This may have been due to extended operation during debugging for data collection. In that instance, the high-side MOSFET showed gate-to-drain continuity, while the low-side MOSFET remained intact. In the other attempts, only the gate driver ICs failed and the MOSFETs were unaffected.

 

◆ Audible noise from inductor appears

Probably the inductor is in saturation. Too much current (and or) too much Voltage X Time.

How much load do you have applied?
Please send the schematic of the power parts. MOSFETs, diodes, inductor/transformers, ....

 

This is one of those cases where a multi channel scope is required, to capture waveforms prior to failure.
Like a previous poster mentioned, the most likely scenario is loop instability.

 

This is one of those cases where a multi channel scope is required, to capture waveforms prior to failure.
Like a previous poster mentioned, the most likely scenario is loop instability.

I think we need to concentrate on what could actually kill a gate driver. My first thoughts were that it could have failed following a MOSFET failure, but if the MOSFETs haven’t failed, I can only think it could be over voltage on the bootstrapped supply. How about putting a zener across the bootstrapped supply? say 12V? Does that solve it? Or does the zener fail?
Loop instability tends to lead to the circuit oscillation at the LC resonant frequency, and doing so can generate a lot of voltage. This is usually prevented by introducing a zero into the feedback of the error amplifier to ensure that there is sufficient phase margin, but I see that there already is a type III compensation network, as would be appropriate for a voltage-mode buck.

 

Now that you mention it Ian;
I now remember an old Unitrode app note which recommended putting reverse biased Schottky diodes from the driver output to ground.
The idea here is that all the parasitic elements where the current flows, could cause a negative spike that would trigger a driver latchup. And a latchup is a scenario which usually ends with an IC’s catastrophic failure.

 

Probably the inductor is in saturation. Too much current (and or) too much Voltage X Time.

How much load do you have applied?
Please send the schematic of the power parts. MOSFETs, diodes, inductor/transformers, ....

We have not applied any load there is a 280 ohm load resistance at the end of output lc filter.Am also attaching the MOSFET and TRANSFORMER part.

 

This is one of those cases where a multi channel scope is required, to capture waveforms prior to failure.
Like a previous poster mentioned, the most likely scenario is loop instability.

Are you infering any incident like voltage spikes.

 

Not only voltage spikes, but double or missing pulses, drive overlapping, that kind of stuff.

 

Maybe more simple: if the high-side MOSFET exceeds the maximum useable time (mainly depends on the capacitance of the bootstrap capacitor), it will slowly transit to non-conducting (as the gate voltage drops over time). During this transistion the conduction losses increase massively, which might well kill the MOSFET. (And no - in many of these cases the driver can no longer switch the MOSFET off as it doesn't have enough energy (voltage) to operate.)
And I could well imagine that the DC/DC controller might try to get more energy into the coil by extending the on period of the high-side MOSFET(s).
So it's important to hard-limit the on-time of the high-side MOSFET(s) to a time span that guarantees that the bootstrap capacitor has not been depleted too much.

Audible noise is a sign of operation - although at a relatively low frequency. No noise = no operation (unless your switching frequency is high enough)

 

If the circuit oscillates from low pwm to high pwm - you can easily generate low voltage spikes on the mid point of the totem pole of the fets - this is well known to kill gate drive IC's, also this instability can cause hard switching in the mosfets which soon leads to a failure.
Without the full and complete circuit to see - it is impossible to give advice on what to change to tame the feedback loop - also we can't see the layout and decoupling. Further 400kHz is only for very experienced power electronics engineers who really know what they are doing - also if you lower to 100kHz, you run the risk of saturating the transformer - unless you keep the max pwm on time to 1/4 of full.

 

There is one more effect common to newbie designs - the power and control layout is so poor that RFI from the power stage gets into the control - greatly upsetting it. ( no snubbers on output diodes is a prime issue - as is turning the mosfets on too fast, lack of decoupling, volt control lines picking up RFI - no proper current sensing . . . ). Having two output inductors in series is unusual as the mid-point will ring like crazy - you need snubbers across both, or RC to gnd.

 

If the circuit oscillates from low pwm to high pwm - you can easily generate low voltage spikes on the mid point of the totem pole of the fets - this is well known to kill gate drive IC's, also this instability can cause hard switching in the mosfets which soon leads to a failure.
Without the full and complete circuit to see - it is impossible to give advice on what to change to tame the feedback loop - also we can't see the layout and decoupling. Further 400kHz is only for very experienced power electronics engineers who really know what they are doing - also if you lower to 100kHz, you run the risk of saturating the transformer - unless you keep the max pwm on time to 1/4 of full.

The compensation network, it was simulated in the analog domain together with the error amplifier. From that simulation, the calculated phase margin was approximately 37°.
Given this phase margin, could this be sufficient to cause the kind of low-PWM to high-PWM oscillation we are observing, along with the resulting midpoint voltage spikes and hard switching behavior in the MOSFETs?

From a magnetic standpoint,at 100Khz the core is operating well within its linear region of the B–H curve, where the effective permeability remains stable and does not collapse due to saturation.

I am sharing the complete circuit schematic for your reference.

 

Maybe more simple: if the high-side MOSFET exceeds the maximum useable time (mainly depends on the capacitance of the bootstrap capacitor), it will slowly transit to non-conducting (as the gate voltage drops over time). During this transistion the conduction losses increase massively, which might well kill the MOSFET. (And no - in many of these cases the driver can no longer switch the MOSFET off as it doesn't have enough energy (voltage) to operate.)
And I could well imagine that the DC/DC controller might try to get more energy into the coil by extending the on period of the high-side MOSFET(s).
So it's important to hard-limit the on-time of the high-side MOSFET(s) to a time span that guarantees that the bootstrap capacitor has not been depleted too much.

Audible noise is a sign of operation - although at a relatively low frequency. No noise = no operation (unless your switching frequency is high enough)

If this mechanism -the bootstrap capacitor discharging during extended high-side on-time - is indeed causing the MOSFET to slowly transition and increasing conduction losses, wouldn’t we expect to see similar effects in open-loop operation as well? In our observations, the instability and ringing mainly appear in closed-loop mode, while open-loop operation seems stable.
Could you kindly advise whether there is something specific about the closed-loop dynamics that would make this effect appear only in that mode?

 

If this mechanism -the bootstrap capacitor discharging during extended high-side on-time - is indeed causing the MOSFET to slowly transition and increasing conduction losses, wouldn’t we expect to see similar effects in open-loop operation as well? In our observations, the instability and ringing mainly appear in closed-loop mode, while open-loop operation seems stable.
Could you kindly advise whether there is something specific about the closed-loop dynamics that would make this effect appear only in that mode?

Closed-loop operation might result in duty-cycles up to 100 % (when attempting to zero the error) while open-loop operation might not reach these extremes. As most signals of the control elements are accessible at the pins: attach an oscilloscope and start to measure instead of forcing us to guess!