I am debugging a DC-DC full-bridge converter where the power stage and gate drive operate correctly in open-loop, but the gate driver ICs repeatedly fail when the control loop is closed. I am looking for insights into what mechanisms could cause this behavior.
System Overview
1. Topology...
I'm building a TDR pulse generator using a single GaN FET (TP65H300G4LSGB) in high-side configuration, driven by NCP51820. The drain is at 40 V, and the source goes through a 50 Ω resistor to GND. Output is taken from the FET source. My Final target is upto 200v.
Pulse specs: ~40 V amplitude...