# Input and output Ripple on DC-DC Buck-Boost converter

#### DThompson

Joined Sep 21, 2021
12
I've designed and built an inverting buck-boost converter, but there is a persistent ripple that occurs on both the input and output voltage waveforms, regardless of input and output capacitor sizing. I initially thought this was due to capacitor ESR, but reducing this by placing capacitors in parallel only slightly helps reduce ripple. Any ideas on how to rectify this? I'm testing at a lower current than designed, so could maybe DCM be causing the voltage ripple?

Image 1 below is the converter output voltage at fsw=100kHz.
Channel 1 of image 2 is the drain-source voltage over the switch and channel 2 is the source voltage, which is an ideal DC when the converter is not connected.

#### ericgibbs

Joined Jan 29, 2010
19,024
hi DT,
A circuit diagram would help.
E

#### DThompson

Joined Sep 21, 2021
12
I've designed and built an inverting buck-boost converter, but there is a persistent ripple that occurs on both the input and output voltage waveforms, regardless of input and output capacitor sizing. I initially thought this was due to capacitor ESR, but reducing this by placing capacitors in parallel only slightly helps reduce ripple. Any ideas on how to rectify this? I'm testing at a lower current than designed, so could maybe DCM be causing the voltage ripple?

Image 1 below is the converter output voltage at fsw=100kHz.
Channel 1 of image 2 is the drain-source voltage over the switch and channel 2 is the source voltage, which is an ideal DC when the converter is not connected.
View attachment 252729
View attachment 252730
I've attached a circuit schematic, the input voltage is applied to the nodes on the left

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#### Papabravo

Joined Feb 24, 2006
21,264
Have you done an AC analysis of the open loop and closed loop responses? What you have is called ringing, which occurs in 2nd order systems, subjected to unit step inputs. It is the interaction beteen in the inductor and the capacitors that you have selected and the absence of damping.

#### crutschow

Joined Mar 14, 2008
34,709
The problem is likely that the input wire impedance is comparable to the capacitor wire impedance, and since those two impedances are in parallel, some of the switching current will always come from the input or go out the output.

How is the circuit constructed?
Is it carefully laid out so all the high current paths are short and direct?
Is the input path in series with short capacitor connections to the input and ground?
Do you have a ground plane?
Switching regulators are inherently noise and require careful layout to minimize the noise escaping to the outside world.

Added inductors in series with the input and output should reduce those current spikes.
Common-mode chokes on the input and output may also help.

#### DThompson

Joined Sep 21, 2021
12
The problem is likely that the input wire impedance is comparable to the capacitor wire impedance, and since those two impedances are in parallel, some of the switching current will always come from the input or go out the output.

How is the circuit constructed?
Is it carefully laid out so all the high current paths are short and direct?
Is the input path in series with short capacitor connections to the input and ground?
Do you have a ground plane?
Switching regulators are inherently noise and require careful layout to minimize the noise escaping to the outside world.

Added inductors in series with the input and output should reduce those current spikes.
Common-mode chokes on the input and output may also help.
Yes all loop sizes are minimized and there is a ground plane. The input capacitor is correctly implemented. I've measured input wire impedance at about 0.1 ohms. and capacitor ESR is about 0.04 ohms. I'll look into the inductors to eliminate noise. Thank you

#### Papabravo

Joined Feb 24, 2006
21,264
I have inferred a possible set of requirements, which may or may not match your actual situation, and produced the a simulation which may be helpful to you. My inferences include an input voltage of +25.6V and an output voltage of -6.16V with resepect to the junction of L1 & C1. I chose a switching frequency of 100 kHz because of the "small" inductor value and my reading of the scope trace. The duty cycle is 20% and, with losses that gets you -6.06VDC. You can see from the inductor current that you are operating in DCM (Discontinuous Conduction Mode). I don't know if that was your intention or not. I specifically used a switch model instead of an actual MOSFET to see if the rining was due to component interactions. There appears to be no evidence for that at the moment. The MOSFET itself has parasitic cpacitances which may or may not be accurately modeled in simulations. That remains to be seen. It is also possible that I have made unwarrented assumptions based only on the schematic fragment you provided. Help me to help you with more information.

#### DThompson

Joined Sep 21, 2021
12
I have inferred a possible set of requirements, which may or may not match your actual situation, and produced the a simulation which may be helpful to you. My inferences include an input voltage of +25.6V and an output voltage of -6.16V with resepect to the junction of L1 & C1. I chose a switching frequency of 100 kHz because of the "small" inductor value and my reading of the scope trace. The duty cycle is 20% and, with losses that gets you -6.06VDC. You can see from the inductor current that you are operating in DCM (Discontinuous Conduction Mode). I don't know if that was your intention or not. I specifically used a switch model instead of an actual MOSFET to see if the rining was due to component interactions. There appears to be no evidence for that at the moment. The MOSFET itself has parasitic cpacitances which may or may not be accurately modeled in simulations. That remains to be seen. It is also possible that I have made unwarrented assumptions based only on the schematic fragment you provided. Help me to help you with more information.

View attachment 252748
Thanks for the explanation, your assumptions are correct and your explanation is helpful. It was initially not my intention to operate in DCM, but the circuit should also be operable at lower currents, so that is a design error on my part. I did increase the inductor inductance to 10uH, which was not reflected in the schematic. I doubt miller capacitance has any effect on the ringing, as the switching signal I've measured appears to be almost perfectly square. If its not from component interactions then could the ringing be due to stray inductance?

#### Papabravo

Joined Feb 24, 2006
21,264
In SMPS (Switched-Mode Power Supplies) in general, it is the undamped interaction of the inductance(s) with ANY cpacitance(s) including lumped components on the board, stray values due to layout or the interelectrode capacitances on the MOSFET. Those capacitances, while small, can interact with inductances independent of the Miller effect. I also wanted to explain the use of an "active" load. When I ran the simulations origianlly the negative voltage across kept increasing, seemingly without limit. The topology of the design seems to work, but it does not match the standard ground referenced approach. Is there some reason why the standard ground referenced approach does not work for you? Compare your design to the following:

#### DThompson

Joined Sep 21, 2021
12
In SMPS (Switched-Mode Power Supplies) in general, it is the undamped interaction of the inductance(s) with ANY cpacitance(s) including lumped components on the board, stray values due to layout or the interelectrode capacitances on the MOSFET. Those capacitances, while small, can interact with inductances independent of the Miller effect. I also wanted to explain the use of an "active" load. When I ran the simulations origianlly the negative voltage across kept increasing, seemingly without limit. The topology of the design seems to work, but it does not match the standard ground referenced approach. Is there some reason why the standard ground referenced approach does not work for you? Compare your design to the following:

View attachment 252756
I used a slightly different topology with the switch on the low side to allow for operation without a high-side driver. The operation should still be the same since the period when the switch conducts and the period where the diode conducts loop equations are the same as the regular topology, or am I incorrect in assuming this?

#### Papabravo

Joined Feb 24, 2006
21,264
I used a slightly different topology with the switch on the low side to allow for operation without a high-side driver. The operation should still be the same since the period when the switch conducts and the period where the diode conducts loop equations are the same as the regular topology, or am I incorrect in assuming this?
No it is just that you have the unclamped side of the inductor going to the common. when the switch turns off and the inductor spikes, the diode will not conduct until the spike reaches 25.6V + one Schottky diode drop. That can't be good for the downstream electronics. Unless I am mistaken and you are using the same ground(common) for both the input and the output.

I was having trouble interpreting what was happening with the active load, so I replaced it with a resistor. I then looked at Vout and Vcom with respect to ground and what did I notice but a crap ton of COMMON MODE RINGING. Your components appear to be interacting big time. This is near the end of the simulation and Vout and Vcom appear to be getting further apart. the voltage should be approximately:

25.6 - (25.6/(1-Dc)) = -7.43 and it has wandered pretty far from that. What am I missing?

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#### DThompson

Joined Sep 21, 2021
12
No it is just that you have the unclamped side of the inductor going to the common. when the switch turns off and the inductor spikes, the diode will not conduct until the spike reaches 25.6V + one Schottky diode drop. That can't be good for the downstream electronics. Unless I am mistaken and you are using the same ground(common) for both the input and the output.

I was having trouble interpreting what was happening with the active load, so I replaced it with a resistor. I then looked at Vout and Vcom with respect to ground and what did I notice but a crap ton of COMMON MODE RINGING. Your components appear to be interacting big time. This is near the end of the simulation and Vout and Vcom appear to be getting further apart. the voltage should be approximately:

25.6 - (25.6/(1-Dc)) = -7.43 and it has wandered pretty far from that. What am I missing?

View attachment 252764
I don't believe you're missing anything. Sorry I'm quite new to SMPS design, what causes the common mode ringing, is it just due to difference between ground potential levels or am I misunderstanding it? And what would be the best way of solving this, common mode chokes at the input and output? Thanks for your help thus far.

#### Papabravo

Joined Feb 24, 2006
21,264
I don't believe you're missing anything. Sorry I'm quite new to SMPS design, what causes the common mode ringing, is it just due to difference between ground potential levels or am I misunderstanding it? And what would be the best way of solving this, common mode chokes at the input and output? Thanks for your help thus far.
I think the more fundamental problem is that with the component values you have chosen, only very heavy loads of several amperes can work with such a small inductor and such a large capacitor, I have redone your circuit slightly, using a high side switch and more reasonable component values. Since the inductor current never drops to zero there is no chance for the ringing to occur. There is still a problem with startup oscillations, but at least the voltage does not wander off uncontrolled. 1000uF is way too big of a capacitor to use.

S1 & V2 can be replaced with a P-channel MOSFET and a BJT switch for the gate.

#### DThompson

Joined Sep 21, 2021
12
I think the more fundamental problem is that with the component values you have chosen, only very heavy loads of several amperes can work with such a small inductor and such a large capacitor, I have redone your circuit slightly, using a high side switch and more reasonable component values. Since the inductor current never drops to zero there is no chance for the ringing to occur. There is still a problem with startup oscillations, but at least the voltage does not wander off uncontrolled. 1000uF is way too big of a capacitor to use.

S1 & V2 can be replaced with a P-channel MOSFET and a BJT switch for the gate.

View attachment 252855
Yeah the problem is I need it to be able to function from about 0.5A-10A of output current regulated at 12V, so I sized a large capacitor to be able to handle the ripple current through the capacitor and to reduce ESR. I agree that the inductor is too small no matter what, not sure what I was thinking with that.

#### Papabravo

Joined Feb 24, 2006
21,264
Yeah the problem is I need it to be able to function from about 0.5A-10A of output current regulated at 12V, so I sized a large capacitor to be able to handle the ripple current through the capacitor and to reduce ESR. I agree that the inductor is too small no matter what, not sure what I was thinking with that.
OK. We are 14 posts in and we finally have an output power requirement of -12V @ 10 Amperes or 120 Watts. This is not really a suitable project for the less experienced designers among us. The power levels alone will require considerable skill in component engineering and board layout. I don't know why I was fooling around with -6V. I don't know if you are doing this for a hobby project or if it is for your employer, but if you are doing this for your employer I strongly recommend that you consider consulting a skilled professional in this type of design.

Your existing design had little to no chance of working over that range of power levels. As soon as you tried to go to a low current consumption that large capacitor had no way to discharge between cycles which is why the voltage was essentialy unconstrained. I'll take another shot at the requirements to see if I can propose a ground referenced design that han handle loads at both end of the range without going sbaliato.

#### DThompson

Joined Sep 21, 2021
12
OK. We are 14 posts in and we finally have an output power requirement of -12V @ 10 Amperes or 120 Watts. This is not really a suitable project for the less experienced designers among us. The power levels alone will require considerable skill in component engineering and board layout. I don't know why I was fooling around with -6V. I don't know if you are doing this for a hobby project or if it is for your employer, but if you are doing this for your employer I strongly recommend that you consider consulting a skilled professional in this type of design.

Your existing design had little to no chance of working over that range of power levels. As soon as you tried to go to a low current consumption that large capacitor had no way to discharge between cycles which is why the voltage was essentialy unconstrained. I'll take another shot at the requirements to see if I can propose a ground referenced design that han handle loads at both end of the range without going sbaliato.
Thanks its for a project. I initially sized the capacitor as 68uF but ended up trying a much larger one with higher ripple current and lower ESR to try and reduce the ripple.

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#### Papabravo

Joined Feb 24, 2006
21,264
Thanks its for a project. I initially sized the capacitor as 68uF but ended up trying a much larger one with higher ripple current and lower ESR to try and reduce the ripple.
Yes, I understand. There are things you can do with a linear supply that you cannot do with an SMPS, especially an open loop SMPS.

#### tindel

Joined Sep 16, 2012
938
Thanks its for a project. I initially sized the capacitor as 68uF but ended up trying a much larger one with higher ripple current and lower ESR to try and reduce the ripple.
Assuming the “much larger” capacitor is also physically larger - then the self inductance will be higher, making it effectively larger impedance at high frequency (that is, resistance over frequency). That’s what is probably causing your voltage spikes.

When designing power supplies, each passive component needs to be viewed as a capacitor, resistor, and inductor across frequency or you have no hope in being successful.

Most power supplies over ~5W need special attention made to every single part in the design. I’ve spent days designing and redesigning the input and output filters of power supplies. So many trade offs. Forget the switch stage.

This should provide some more in depth understanding.

#### tindel

Joined Sep 16, 2012
938
Also don’t forget to properly probe for high speed signals to measure accurate magnitudes.

#### Papabravo

Joined Feb 24, 2006
21,264
I have updated my last schematic with the new requirements articulated in post #14. I do not represent that this is either a good or final design, but it is a starting point for your further investigations,

With an unregulated inverting buck-boost converter having a fixed ducty cycle this is the best I can do. The heavier the current draw more the output voltage will stray from the design value of -12V. I have also given the input supply a turn on ramp so the converter doesn't have to deal with a step function on the input. You can move the straight line curves up or down by picking a different compromise duty cycle somewhere in the range of 0.31-0.35 approximately. I chose 0.3275 for a dutycycle for the lowest current of 0.5 A in the load. Notice that the inductor currents will always be larger than the load currents. As a side note, I would expect 14A to saturate many cores that you might choose to fabricate thei inductor so choose your components carefully. Note again that vout is ground referenced and I have modeled the use of a high side switch, neither side of which is connected to ground.

Lastly I have included the LTspice schematic file in case anybody else wants totake a crack at this problem.

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