Just leave off the Vcc connection.
I have seen a thought experiment very similar to this with two capacitors of identical value, one is charged to 100V, the other discharged.
Then they are connected together, and the charge is evenly distributed so the voltage on them both is 50V.
But what happened to the energy? (0.5C V^2)
Half of it disappeared in the process.

Well that’s 50% efficient then. I assume it disappears as heat.

With my ‘thought’ experiment, I suppose if one left the Vcc in place then it would be a repeating process with the capacitor discharging and then charging up and so on. Would the effective RC constant determine the frequency of the repeating cycle?

 

Well that’s 50% efficient then. I assume it disappears as heat.

With my ‘thought’ experiment, I suppose if one left the Vcc in place then it would be a repeating process with the capacitor discharging and then charging up and so on. Would the effective RC constant determine the frequency of the repeating cycle?

One would assume that Vcc would have negligible source impedance, so that the capacitor would not discharge.

 

One would assume that Vcc would have negligible source impedance, so that the capacitor would not discharge.

Another fly in the ‘ointment’. If I remember rightly (becoming a long while back), my original circuit had two switches and when S1 was closed then the cap charged up and then in my description I opened S1 (to disconnect from Vcc) and then I closed S2 to connect to the battery. In that case I should keep Vcc and just put back in my first switch. Then one can open and close S1 as fast as desired to enact the scenario originally proposed. I will redraw and post in a short while.

 

This circuit more accurately reflects my original proposal. Once a discharge has been completed then one can close S1 again and start a new cycle. Of course the FET trigger would be coordinated to open Q2 at the appropriate time.



I am reminded of what DickCappels said at the beginning: "A lot of trouble for no benefit" - but it illustrates lots of issues for my student. And to them I think I can confidently say - " I wouldn't worry about it, matching the resistances serves little purpose"

 

You have your parts arranged funny and you are missing a diode. This is a simplified schematic of a buck converter. I advocate using a P-channel MOSFET with the source and drain swapped from that shown, that may simplify the gate drive circuit.

 

You have your parts arranged funny and you are missing a diode. This is a simplified schematic of a buck converter. I advocate using a P-channel MOSFET with the source and drain swapped from that shown, that may simplify the gate drive circuit.
View attachment 289412

Ah, the diode is in parallel with the inductor and not series. Apparently, from previous posts, I should be using a Buck-Boost converter to deal with when the capacitor drops below the battery voltage but does it need to as I assume the capacitor can just discharge down to the battery voltage and stop there?

With the P-FET, you are suggesting that the voltage source is connected to the Drain instead of the Source as I have it?

With these revisions, I take it the only limitation is how big the inductor is in terms of how high the voltage source can be and the peak current. It would seem that the Buck-Boost option would tend towards a max 25V, 10A from what I have seen of various device specs.

 

As we are dealing with a single pulse, many of the switched-mode design rules don’t apply.
The higher the inductance, the slower the rise of current, and the lower the peak value.
You can work it out as a 2nd order differential equation, or you can let SPICE simulate it for you.

 

Going down the Spice route is probably more time than the original query warrants but I take the point.

Here is the 'improved' circuit. I expect I may still have the P-FET connections the wrong way round as the symbol in post 65 is not quite what my toolbox provides.

I wonder if the sequence of events for the energy transfer is the same as when the capacitor and P-FET switch positions were reversed, as in earlier simulations?

 

Here is the 'improved' circuit. I expect I may still have the P-FET connections the wrong way round

Yes.
A MOSFET has a substrate diode which conducts in the direction of the arrow, so you need to reverse the source and drain in your drawing.
The 30V comes from your charged capacitor.
For charging a battery, C1 is not needed.
That circuit will only discharge the capacitor down to the battery voltage.

 

Yes.
A MOSFET has a substrate diode which conducts in the direction of the arrow, so you need to reverse the source and drain in your drawing.
The 30V comes from your charged capacitor.
For charging a battery, C1 is not needed.
That circuit will only discharge the capacitor down to the battery voltage.

So I had them right the first time in #64 with the P-FET the Source is at the top in my earlier drawing so that was correct. I did wonder.

Ok re the capacitor but that was at the centre of the initial query.

Can anyone explain why switching around the capacitor and FET does a better job of the discharge than the earlier format that was Spice simulated?

 

Using a P-channel MOSFET allows you to drive the gate from the source voltage to ground instead of having to generate a gate voltage higher than the source voltage, and still have the MOSFET in saturation while on. If you drive the gate and take the output from the source you would have a voltage follower in which the output voltage will be lower than the gate voltage.

 

Using a P-channel MOSFET allows you to drive the gate from the source voltage to ground instead of having to generate a gate voltage higher than the source voltage, and still have the MOSFET in saturation while on. If you drive the gate and take the output from the source you would have a voltage follower in which the output voltage will be lower than the gate voltage.

But I already had a P channel FET in #64 with its Source connected to the Diode cathode.

And why does swapping the positions of the capacitor and FET improve on the way the charged capacitor discharges to the battery, as per the design proposed by others and LTSpice simulated. I’m more confused than when I started.

 

But I already had a P channel FET in #64 with its Source connected to the Diode cathode.

And why does swapping the positions of the capacitor and FET improve on the way the charged capacitor discharges to the battery, as per the design proposed by others and LTSpice simulated. I’m more confused than when I started.

The diode allows current to continue to flow after the MOSFET switches off, thus transferring all the energy stored in the inductor to the output.

 

The diode allows current to continue to flow after the MOSFET switches off, thus transferring all the energy stored in the inductor to the output.

I hear you but then how come the Spice simulation seemed to work fine, or was it limited by the positions of the capacitor and FET?

 

Hi T88,
In the sims , do the caps have an ESR component.?
Also, it is common in smps to use lower value caps in parallel to make up the required total vale, thus the total ESR value is lower.

IE, say for example 4 * 250uF with each say 100mΩ, so 25mΩ effective.

E

 

Hi T88,
In the sims , do the caps have an ESR component.?
Also, it is common in smps to use lower value caps in parallel to make up the required total vale, thus the total ESR value is lower.

IE, say for example 4 * 250uF with each say 100mΩ, so 25mΩ effective.

E

I don't know as I have never done a Spice sim. That would be a lot of time and effort to address my student's question. Might be something I do in the future though.

I thought one of the conclusions was that ESR is irrelevant to the efficiency of the discharge and only affects the rate of energy flow? (e.g. post 24)

So is the circuit below the most efficient way to transfer the energy from the capacitor to the battery (with a voltage drop of 30V to 12V):

It was said that "Due to the MOSFET substrate diode, you still need the Schottky diode in series to block the reverse current flow." So is the diode placement here in parallel still doing its blocking? It would seem so.

 

generate a gate voltage higher than the source voltage, and still have the MOSFET in saturation while on.

This is a nit, but to confuse us as compared to BJTs, they decided to call the active region in a MOSFET the saturation region.
Fully on is in the linear region.

 

But I already had a P channel FET in #64 with its Source connected to the Diode cathode.

Yes, that configuration if fine for the one-shot resonant charge.
Some of the other circuits are illustrating a buck regulator, which is a slightly different animal.

From post #76

So is the circuit below the most efficient way to transfer the energy from the capacitor to the battery (with a voltage drop of 30V to 12V):

Not if the capacitor is C1, since that capacitor voltage always equals the battery voltage.

 

Yes, that configuration if fine for the one-shot resonant charge.
Some of the other circuits are illustrating a buck regulator, which is a slightly different animal.

From post #76Not if the capacitor is C1, since that capacitor voltage always equals the battery voltage.

Surely only when the P-FET is open and that will only occur when the cap is being charged up. Once it has reached full charge then the original idea was to discharge it most efficiently. My original proposition was that the second switch to discharge the capacitor was a P-FET but over time it seems the whole design has been shifted to something else.

I think I need to return to one of the earlier designs like in #57.