Hi,
I am simulating my postgraduate project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is there any way to do that?
Thanks
I am simulating my postgraduate project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is there any way to do that?
Thanks