1. J

    How to adjust PCIE signals using Hyperlynx S- Parameter report?

    Dear All, I’m using Hyperlynx (MentorGraphic) for Signal Integrity test for PCIE GEN 1 Tx Rx & Clk signals. I imported Altium designed layout file to Hyperlynx. This signals (Tx, Rx, Clk) don’t pass S – Parameters when I run Serdes Batch Wizard. But it pass Channel Verification. 1) What are...
  2. E

    How to change trace width and spacing of diff pairs in the design using MentorGraphics Hyperlynx SI

    Hi, I am simulating my postgraduate project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is...