trace width

Hi all, I have a 4-layer PCB with a below layer-stack and I will be having a net that is supposed to handle 100A. I know I should use a heavy copper PCB instead of this 4-layer PCB but to save cost I stitched 4 polygons on all layers with (0.5 hole size, 1 diameter) vias to accommodate the high...

I'm building a board with multiple ASIC's in series. Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC. In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain. Further, these ASIC's are...

Please see https://electronics.stackexchange.com/questions/610932/power-circuit-for-tb9051ftg-trace-width If anyone could offer more advice about the trace width I should be using for the power circuit for the TB9051FTG chip, that would be hugely helpful.

Hi, I am simulating my postgraduate project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is...