I'm building a board with multiple ASIC's in series. Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC. In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain. Further, these ASIC's are connected in series, such that V- for one chip is connected to V+ for the next. The specs for this chip say that it can draw up to 45A.

The V+ and V- pads on this chip are 325 mils wide (150 mils tall). In order to carry this much current from one chip to another, I'm using 4 layers of 2oz/sqft copper, with an array of vias directly in the pads. Using PCB trace width calculators, I'm estimating that if I stretch a 325 mil wide trace/pour between the pads in all four layers, then the 2 inner layers should be able to carry approximately 9A each, while the external layers could carry approximately 18A each, for a total current capacity of 54A, assuming a maximum desired temperature change of 10 degrees C.

However, I'm trying to stick to a 4 layer board. The design I described above means that I do not have ground planes adjacent to these traces.

• Is that bad or very bad?
• What are my alternatives?
• Must I add more layers, and if so, what stack up would you recommend?
• Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current? For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative? I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.

Any advice you can give is appreciated. What would your thought process be in beginning layout for such a design? What considerations have I missed?

 

In the past I usually dealt with high currents using bus bars.

https://en.m.wikipedia.org/wiki/Busbar

 

these ASIC's are connected in series, such that V- for one chip is connected to V+ for the next.

What? V+ is connected to V-? Why? So the bottom IC gets 3V and 0V, The one on top gets 6V and 3V. Then 9V and 6V. 12 and 9V? I hope I don't understand.
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"45A" for 1nS. Not long time draw. I cannot see your PCB. Use a trace the size of the pad and get to a capacitor as soon as possible. That is where the high current is coming from. Then you can worry about where the DC current is coming from. More like 1A or less.

 

In the past I usually dealt with high currents using bus bars.

https://en.m.wikipedia.org/wiki/Busbar

Thanks for the feedback. I've considered this, but I'm not really sure how to implement it on a PCB. I've seen busbars used to go board to board. Are you aware of any small, solder-down busbars that would be ~1cm square? If so, could you recommend a vendor or part number?

 

What? V+ is connected to V-? Why? So the bottom IC gets 3V and 0V, The one on top gets 6V and 3V. Then 9V and 6V. 12 and 9V? I hope I don't understand.
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"45A" for 1nS. Not long time draw. I cannot see your PCB. Use a trace the size of the pad and get to a capacitor as soon as possible. That is where the high current is coming from. Then you can worry about where the DC current is coming from. More like 1A or less.

Unfortunately what I described is true. No, this is not a short in-rush current. We expect 35A average, 45A max. Stacking compute chips in series is common (ironically to limit current) in some applications. I've just never had to design something like this myself.

 

Thanks for the feedback. I've considered this, but I'm not really sure how to implement it on a PCB. I've seen busbars used to go board to board. Are you aware of any small, solder-down busbars that would be ~1cm square? If so, could you recommend a vendor or part number?

The busbars of which I was familiar were long and went across PC boards distributing power. In many circuit they were there to keep the power to circuits stable in spite of high transient currents. The were more about impedance than mere resistance and if used carefully could greatly reduce the number of bypass capacitors need in say, a memory board of the day (1980's and thereabouts).

They were about 20 cm long more of less and maybe 1 cm tall with solder legs to connect to the PCB every few CM - usually set to have one connection of each of the memory chips if a row or column.

A different kind of busbar is used for distributing high AC or DC current. They can be custom designed from stampings to connect as few as two points on a PCB so that the cladding on the board would not have to handle the current.

I would not feel comfortable recommending a specific part but I am pretty sure that Rogers Corporation is a good place to start looking.

 

How are you going to keep the voltage across each ASIC constant? When stacking loads (series) the loads should be exactly the same to keep the voltage to be the same.
What is the supply voltage. A 2 volt part at 45A is 50 watts. (each) Have you thought about how to get the heat out.

I will find some examples of ASIC PCB layouts. Time permitting.

 

How are you going to keep the voltage across each ASIC constant? When stacking loads (series) the loads should be exactly the same to keep the voltage to be the same.
What is the supply voltage. A 2 volt part at 45A is 50 watts. (each) Have you thought about how to get the heat out.

I will find some examples of ASIC PCB layouts. Time permitting.

Yes, obviously heat management is an important part of the design. These chips do not require regulators across each chip, but I also was worried about the same thing. Apparently, they act more like resistive loads. I am not too knowledgeable about how they pull this off at the chip level, but I know that no regulators are required to control the voltage across each chip. Wiring them directly to the next chip is the intended arrangement for these chips.

 

ICs that I use pull wildly different amounts of current depending on what they are doing. This will not be good for dividing up the supply across 4 ICs.