layout

I'm building a board with multiple ASIC's in series. Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC. In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain. Further, these ASIC's are...

I want to convert ISCAS benchmark's (for example c17 , c432) Verilog files to gds files (gate level to gds conversion). Also, I have to use the open-source standard cells NANGATE45. Is there any open source tool for gate-level to gds converter which can be done with NANGATE45?

Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: - DRC (Design Rule Check) checks if a laid out block follows technology rules what ensures dimensional precision and electrical parameters - DFM (Design For Manufacturing)...

Hi, As you can see from the attached picture, I used some polygon area on the top side. Anyway, the surface has some empty zone close to pad that I would like to fill with copper. Do you know how to do that? Thank you.

Hello! If you need a PCB designer to help you with one of your projects, then I may be able to help! I'm offering my services at a low cost at the moment, so hopefully this proposition is interesting! I've been in the electronics industry for approximately 3-years at this point and over that...

Dear All, I’m using Hyperlynx (MentorGraphic) for Signal Integrity test for PCIE GEN 1 Tx Rx & Clk signals. I imported Altium designed layout file to Hyperlynx. This signals (Tx, Rx, Clk) don’t pass S – Parameters when I run Serdes Batch Wizard. But it pass Channel Verification. 1) What are...